PRELIMINARY
CYP15G0402DX
Pin Descriptions
Quad HOTLink II SERDES
Name
I/O Characteristics
Signal Description
Transmit Path Data Signals
TXPERA
TXPERB
TXPERC
TXPERD
LVTTL output,
changes following
TXCLKO↑
Transmit Path Parity Error. Active HIGH parity checking must be enabled and a parity
error will be detected. This output is HIGH for one TXCLKO± clock period to indicate
detection of a parity error in the character presented to the shifter. When parity error is
detected, the character in error is replaced with a +C0.7 character to force a corre-
sponding bad character detection at the remote end of the link. This replacement takes
place only when parity checking is enabled (PARCTL ≠ LOW). When BIST is enabled
for a transmit channel, BIST progress is presented on the associated TXPERx output.
Once every 511 character times, TXPERx pulses HIGH for one TXCLKO± period to
indicate a complete pass through the BIST sequence. When the transmit Phase Align
Buffers are enabled (TXCKSEL ≠ LOW), if an underflow or overflow condition is
detected, TXPERx for that channel is asserted and remains asserted until reset by
TXRST.
TXDA[9:0]
TXDB[9:0]
TXDC[9:0]
TXDD[9:0]
LVTTL input,
synchronous,
sampled by the
respectiveTXCLKx↑
or TXCLKO↑
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
interface clock and passed to the transmit shifter. TXDx[9:0] specify the specific trans-
mission character to be sent.
TXOPA
TXOPB
TXOPC
TXOPD
LVTTL input,
synchronous,
sampled by the
respectiveTXCLKx↑
or TXCLKO↑
Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the
ODD parity captured at these inputs is XORed with the bits on the associated TXDx bus
to verify the integrity of the captured character.
Transmit Path Clock and Control
TXCLKO±
LVTTL output
Transmit Clock Output. This true and complement clock is synthesized by the transmit
PLL and is synchronous to the internal transmit character clock. It operates at either the
same frequency as REFCLK, or at twice the frequency of REFCLK. TXCLKO± is always
equal to the VCO bit-clock frequency ÷10. The TXCLKO+ output rising edges and
TXCLKO– falling edges are phase aligned to the rising edges of the REFCLK input.
TXRST
LVTTL Input,
asynchronous
Transmit Clock Phase Reset, active LOW. When LOW, the transmit Phase Align
Buffers are allowed to adjust their data transfer timing to allow clean transfer of data from
the Input Register to the transmit shifter. When TXRST is HIGH, the internal phase
relationship between the selected TXCLKx and the internal character-rate clock is fixed.
During this reset alignment period, one or more characters may be added to or lost from
all the associated transmit paths as the transmit elasticity buffers are adjusted.
TXCKSEL
TXRATE
3-Level Select[1]
Transmit Clock Select. Selects the clock source used to write data into the transmit
Static Control Input Input Register. When LOW, all four input registers are clocked by the internal TXCLKO↑
derivative of REFCLK. When TXCKSEL is MID, TXCLKx↑ is used as the input register
clock for the associated TXDx[9:0] and TXOPx. When HIGH, TXCLKA↑ is used to clock
data into the input register for all channels.
LVTTL Input,
asynchronous,
internal pull-up
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies
REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit
PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See Table 3 for a list
of operating serial rates.
When REFCLK is selected for clocking of the receive parallel interfaces, the TXRATE
input also determines if the clock on the RXCLKA± and RXCLKC± outputs is a full or
half-rateclock. When TXRATE =HIGH, theseclocks arehalf-rateclocks. WhenTXRATE
= LOW, these output clocks are full-rate clocks and follow the frequency and duty cycle
of the REFCLK input.
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input Transmit Path Input Clocks. These inputs are only used when TXCKSEL ≠ LOW.
asynchronous,
These clocks are frequency coherent to TXCLKO±, but may be offset in phase.
Operating phase is adjusted when TXRST is LOW; and phase locked when TXRST is
HIGH.
internal pull-up
Document #: 38-02023 Rev. *B
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