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CYP15G0402DX-BGC PDF预览

CYP15G0402DX-BGC

更新时间: 2024-02-16 09:43:06
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 电信集成电路电信电路信息通信管理
页数 文件大小 规格书
27页 818K
描述
Quad HOTLinkII SERDES

CYP15G0402DX-BGC 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256针数:256
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:27 mm湿度敏感等级:3
功能数量:1端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA256,20X20,50封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:1.5,3.3 V认证状态:Not Qualified
座面最大高度:1.745 mm子类别:Other Telecom ICs
标称供电电压:3.3 V表面贴装:YES
技术:BICMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:27 mmBase Number Matches:1

CYP15G0402DX-BGC 数据手册

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PRELIMINARY  
CYP15G0402DX  
Document Title: CYP15G0402DX Quad HOTLinkIISERDES  
Document Number: 38-02023  
Issue  
Orig. of  
Change  
REV.  
**  
ECN NO. Date  
Description of Change  
108363  
108915  
112986  
07/11/01  
TME  
AMV  
TPS  
New Data Sheet  
*A  
*B  
07/31/01  
03/01/02  
Changed name of part from PHY to SERDES  
Changed common mode input specs to match 401D part pp. 17, 18  
Added engineering changes to half-rate timing. p. 22  
Updated the spec as per meeting with engineering pp. 2023  
Changed the Refclock input to VLTTL both inputs p. 9  
Addition of TXCLKO N and the TXCLKO P specs p. 22  
Changed the TXCLKO clock output to reflect the new timing p. 22  
Changed the Half Clock drawing so that the valid time was at clock edges  
Changed the input power input p. 21, p. 22 max. power  
Changed the spec for serial output levels at the different terminations.  
Changed the common mode input range of serial input  
Increased the serial input current under the conditions of VCC and min.  
Added to the duty cycle of transmit and receiver clock signals  
Changed rise time of the serial inputs and receiver  
Changed half-rate timing drawing from not valid at clock edges to valid at  
clock edges  
Max. voltage reduced from 4.2 to 3.8  
Matched the common specs with the family of parts pp. 2124  
Changed max output current to 35 Ma p. 20  
Corrected period timing of min. clock from 100 ns to 50 ns p. 19  
Added Preliminary”  
Added pin RXCKSEL to the pin layout p. 6, 7 to pin layout and pin descriptions  
Change min. clock frequency  
Change the front pages  
Remove decoder command from p. 16, as it is no longer used.  
Document #: 38-02023 Rev. *B  
Page 27 of 27  

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