Datasheet > CYK256K16MCCB

CYK256K16MCCB

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	387K
描述
4-Mbit (256K x 16) Pseudo Static RAM

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CYK256K16MCCB 数据手册

CYK256K16MCCB

MoBL3™

AC Test Loads and Waveforms

ALL INPUT PULSES

90%

10%

V_CC

OUTPUT

V_CC

GND

90%

10%

Fall Time = 1 V/ns

30 pF

Rise Time = 1 V/ns

Equivalentto:

INCLUDING

JIG AND

SCOPE

THÉVENINEQUIVALENT

R_TH

OUTPUT

V_TH

Parameters

3.0V V_CC

22000

11000

1.50

Unit

Ω

R_TH

V_TH

Ω

Switching Characteristics Over the Operating Range^[10]

55 ns^[14]

60 ns

Max.

70 ns

Max.

Parameter

Read Cycle

Description

Min.

Max.

Min.

Unit

t_RC

Read Cycle Time

t_AA

Address to Data Valid

t_OHA

t_ACE

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_DBE

t_LZBE

t_HZBE

Data Hold from Address Change

CE LOW to Data Valid

OE LOW to Data Valid

OE LOW to LOW Z^{[11, 13]}

OE HIGH to High Z^{[11, 13]}

CE LOW to Low Z^{[11, 13]}

CE HIGH to High Z^{[11, 13]}

BLE/BHE LOW to Data Valid

BLE/BHE LOW to Low Z^{[11, 13]}

BLE/BHE HIGH to HIGH Z^{[11, 13]}

Address Skew

[14]

t_SK

Write Cycle^[12]

t_WC

t_SCE

t_AW

t_HA

Write Cycle Time

CE LOW to Write End

Address Set-Up to Write End

Address Hold from Write End

Address Set-Up to Write Start

WE Pulse Width

t_SA

t_PWE

Notes:

10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V

/2, input pulse levels

CC(typ)

of 0V to V

, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.

CC(typ.)

OL OH

11. t

, t

, and t

transitions are measured when the outputs enter a high impedance state.

HZOE HZCE HZBE

HZWE

12. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any

of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates

the write.

13. High-Z and Low-Z parameters are characterized and are not 100% tested.

14. To achieve 55-ns performance, the read access should be CE controlled. In this case t

is the critical parameter and t is satisfied when the addresses are

ACE

stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.

Document #: 38-05585 Rev. *F

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与CYK256K16MCCB相关器件

型号	品牌	描述	获取价格	数据表
CYK256K16MCCB-60BVI	CYPRESS	Pseudo Static RAM, 256KX16, 60ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48	获取价格
CYK256K16MCCB-70BVI	CYPRESS	Pseudo Static RAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48	获取价格
CYK256K16MCCBU-55BVI	CYPRESS	4-Mbit (256K x 16) Pseudo Static RAM	获取价格
CYK256K16MCCBU-55BVXI	CYPRESS	Pseudo Static RAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48	获取价格
CYK256K16MCCBU-60BVI	CYPRESS	4-Mbit (256K x 16) Pseudo Static RAM	获取价格
CYK256K16MCCBU-70BVI	CYPRESS	4-Mbit (256K x 16) Pseudo Static RAM	获取价格

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