5秒后页面跳转
CYDC064B16-55BVXC PDF预览

CYDC064B16-55BVXC

更新时间: 2024-01-14 12:42:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
26页 819K
描述
Dual-Port SRAM, 4KX16, 55ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100

CYDC064B16-55BVXC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.78
最长访问时间:55 ns其他特性:ALSO OPERATES AT 2.5V AND 3V SUPPLY
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX16封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

CYDC064B16-55BVXC 数据手册

 浏览型号CYDC064B16-55BVXC的Datasheet PDF文件第4页浏览型号CYDC064B16-55BVXC的Datasheet PDF文件第5页浏览型号CYDC064B16-55BVXC的Datasheet PDF文件第6页浏览型号CYDC064B16-55BVXC的Datasheet PDF文件第8页浏览型号CYDC064B16-55BVXC的Datasheet PDF文件第9页浏览型号CYDC064B16-55BVXC的Datasheet PDF文件第10页 
CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
When reading a semaphore, all sixteen/eight data lines output  
the semaphore value. The read value is latched in an output  
register to prevent the semaphore from changing state during  
a write from the other port. If both ports attempt to access the  
semaphore within tSPS of each other, the semaphore will  
definitely be obtained by one side or the other, but there is no  
guarantee which side will control the semaphore. On  
power-up, both ports should write “1” to all eight semaphores.  
CYDC128B08 consist of an array of 8K and 16K words of 8  
each of dual-port RAM cells, I/O and address lines, and control  
signals (CE, OE, R/W).These control pins permit independent  
access for reads or writes to any location in memory. To handle  
simultaneous writes/reads to the same location, a BUSY pin is  
provided on each port. Two Interrupt (INT) pins can be utilized  
for port-to-port communication. Two Semaphore (SEM)  
control pins are used for allocating shared resources. With the  
M/S pin, the devices can function as a master (BUSY pins are  
outputs) or as a slave (BUSY pins are inputs). The devices  
also have an automatic power-down feature controlled by CE.  
Each port is provided with its own output enable control (OE),  
which allows data to be read from the device.  
Architecture  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
CYDC128B08, CYDC064B08 consist of an array of 4K, 8K, or  
16K words of 16 dual-port RAM cells, I/O and address lines,  
and control signals (CE, OE, R/W). The CYDC064B08 and  
Table 1. Non-Contending Read/Write  
Inputs  
Outputs  
[11]  
CE  
H
X
L
R/W  
X
OE  
X
X
X
X
X
L
UB  
X
H
L
LB  
X
H
H
L
SEM I/O8I/O15  
I/O0I/O7  
High Z  
Operation  
Deselected: Power-down  
Deselected: Power-down  
Write to Upper Byte Only  
Write to Lower Byte Only  
Write to Both Bytes  
H
H
H
H
H
H
H
H
X
L
High Z  
X
High Z  
High Z  
L
Data In  
High Z  
High Z  
L
L
H
L
Data In  
Data In  
High Z  
L
L
L
Data In  
Data Out  
High Z  
L
H
H
H
X
L
H
L
Read Upper Byte Only  
Read Lower Byte Only  
Read Both Bytes  
L
L
H
L
Data Out  
Data Out  
High Z  
L
L
L
Data Out  
High Z  
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled  
H
H
Data Out  
Data Out  
Data In  
Data Out  
Data Out  
Data In  
Read Data in Semaphore Flag  
Read Data in Semaphore Flag  
Write DIN0 into Semaphore Flag  
L
L
X
L
X
X
H
H
L
Data In  
Data In  
Write DIN0 into Semaphore Flag  
L
L
X
X
X
X
L
X
L
L
L
Not Allowed  
Not Allowed  
X
Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[12]  
Left Port  
Right Port  
Function  
R/WL CEL  
OEL  
X
A0L–13L  
3FFF[15]  
X
INTL R/WR CER OER  
A0R–13R  
X
3FFF[15]  
3FFE[15]  
X
INTR  
L[14]  
H[13]  
X
Set Right INTR Flag  
Reset Right INTR Flag  
Set Left INTL Flag  
Reset Left INTL Flag  
L
X
X
X
L
X
X
L
X
X
X
L
X
L
X
L
X
X
X
X
L[13]  
H[14]  
L
X
X
L
3FFE[15]  
X
X
X
Notes:  
11. This column applies to x16 devices only.  
12. See Interrupts Functional Description for specific highest memory locations by device.  
13. If BUSY = L, then no change.  
R
14. If BUSY = L, then no change.  
L
15. See Functional Description for specific addresses by device.  
Document #: 001-01638 Rev. *C  
Page 7 of 26  

与CYDC064B16-55BVXC相关器件

型号 品牌 描述 获取价格 数据表
CYDC064B16-55BVXI CYPRESS Dual-Port SRAM, 4KX16, 55ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC

获取价格

CYDC128B08 CYPRESS 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

获取价格

CYDC128B08-40AXC CYPRESS 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

获取价格

CYDC128B08-40BVXC CYPRESS Dual-Port SRAM, 16KX8, 40ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC

获取价格

CYDC128B08-55AXC CYPRESS 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

获取价格

CYDC128B08-55AXI CYPRESS 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

获取价格