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CYDC064B16-55BVXC PDF预览

CYDC064B16-55BVXC

更新时间： 2024-01-01 02:57:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
26页 819K
描述
Dual-Port SRAM, 4KX16, 55ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100

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CYDC064B16-55BVXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：100
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.78
最长访问时间：55 ns其他特性：ALSO OPERATES AT 2.5V AND 3V SUPPLY
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
长度：14 mm内存密度：65536 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：100字数：4096 words
字数代码：4000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4KX16封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

CYDC064B16-55BVXC 数据手册

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CYDC256B16, CYDC128B16,  
CYDC064B16, CYDC128B08,  
CYDC064B08  
Pin Definitions  
Left Port  
CEL  
Right Port  
CER  
Description  
Chip Enable  
R/WL  
R/WR  
Read/Write Enable  
Output Enable  
OEL  
OER  
A0L–A13L  
I/O0L–I/O15L  
SEML  
A0R–A13R  
I/O0R–I/O15R  
SEMR  
UBR  
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices).  
Data Bus Input/Output for x16 devices; I/O0–I/O7 for x8 devices.  
Semaphore Enable  
UBL  
Upper Byte Select (I/O8–I/O15 for x16 devices; Not applicable for x8 devices).  
Lower Byte Select (I/O0–I/O7 for x16 devices; Not applicable for x8 devices).  
Interrupt Flag  
LBL  
LBR  
INTL  
INTR  
BUSYL  
BUSYR  
Busy Flag  
IRR0, IRR1  
Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16.  
A13L, A13R for CYDC256B16 and CYDC128B08 devices.  
ODR0-ODR4  
SFEN  
M/S  
Output Drive Register; These outputs are Open Drain.  
Special Function Enable  
Master or Slave Select  
VCC  
Core Power  
GND  
Ground  
VDDIOL  
VDDIOR  
NC  
Left Port I/O Voltage  
Right Port I/O Voltage  
No Connect. Leave this pin Unconnected.  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
Functional Description  
CYDC128B08, CYDC064B08 are available in 100-pin TQFP  
The  
CYDC256B16,  
CYDC128B16,  
CYDC064B16,  
packages.  
CYDC128B08, CYDC064B08 are low-power CMOS 4K,  
8K,16K x 16, and 8/16K x 8 dual-port static RAMs. Arbitration  
schemes are included on the devices to handle situations  
when multiple processors access the same piece of data. Two  
ports are provided, permitting independent, asynchronous  
access for reads and writes to any location in memory. The  
devices can be utilized as standalone 16-bit dual-port static  
RAMs or multiple devices can be combined in order to function  
as a 32-bit or wider master/slave dual-port static RAM. An M/S  
pin is provided for implementing 32-bit or wider memory appli-  
cations without the need for separate master and slave  
devices or additional discrete logic. Application areas include  
interprocessor/multiprocessor designs, communications  
status buffering, and dual-port video/graphics memory.  
Power Supply  
The core voltage (VCC) can be 1.8V, 2.5V or 3.3V, as long as  
it is lower than or equal to the I/O voltage.  
Each port can operate on independent I/O voltages. This is  
determined by what is connected to the VDDIOL and VDDIOR  
pins. The supported I/O standards are 1.8V/2.5V LVCMOS  
and 3.0V LVTTL.  
Write Operation  
Data must be set up for a duration of tSD before the rising edge  
of R/W in order to guarantee a valid write. A write operation is  
controlled by either the R/W pin (see Write Cycle No. 1  
waveform) or the CE pin (see Write Cycle No. 2 waveform).  
Required inputs for non-contention operations are summa-  
rized in Table 1.  
Each port has independent control pins: Chip Enable (CE),  
Read or Write Enable (R/W), and Output Enable (OE). Two  
flags are provided on each port (BUSY and INT). BUSY  
signals that the port is trying to access the same location  
currently being accessed by the other port. The Interrupt flag  
(INT) permits communication between ports or systems by  
means of a mail box. The semaphores are used to pass a flag,  
or token, from one port to the other to indicate that a shared  
resource is in use. The semaphore logic is comprised of eight  
shared latches. Only one side can control the latch  
(semaphore) at any time. Control of a semaphore indicates  
that a shared resource is in use. An automatic power-down  
feature is controlled independently on each port by a Chip  
Enable (CE) pin.  
If a location is being written to by one port and the opposite  
port attempts to read that location, a port-to-port flowthrough  
delay must occur before the data is read on the output;  
otherwise the data read is not deterministic. Data will be valid  
on the port tDDD after the data is presented on the other port.  
Read Operation  
When reading the device, the user must assert both the OE  
and CE pins. Data will be available tACE after CE or tDOE after  
OE is asserted. If the user wishes to access a semaphore flag,  
Document #: 001-01638 Rev. *C  
Page 5 of 26  
12345678...26

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CYDC128B08-55AXI CYPRESS 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

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