MB9B360R Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
The MB9B360R Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
competitive cost.
These series are based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).
Features
[SRAM]
32-bit ARM® Cortex®-M4F Core
This is composed of three independent SRAMs (SRAM0,
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
SRAM1 and SRAM2). SRAM0 is connected to I-code bus or
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
SRAM0: Up to 64 Kbytes
SRAM1: Up to 32 Kbytes
SRAM2: Up to 32 Kbytes
Support DSP instruction
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-bit Data width
24-bit System timer (Sys Tick): System timer for OS task
management
Up to 25-bit Address bit
On-chip Memories
Maximum Access size: 256M byte
Supports Address/Data multiplex
Supports external RDY function
Supports scramble function
[Flash memory]
These series are based on two independent on-chip Flash
memories.
MainFlash memory
Up to 1024 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
Possible to set the validity/invalidity of the scramble function
for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4
Mbytes units.
buffer memory
The read access to Flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to Flash memory can be obtained by
Flash Accelerator System.
Possible to set two kinds of the scramble key
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
Security function for code protection
USB Interface
USB interface is composed of Device and Host.
WorkFlash memory
32 Kbytes
Read cycle:
• 6 wait-cycle: the operation frequency more than 120
MHz, and up to 160 MHz
[USB device]
USB2.0 Full-Speed supported
• 4 wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
Max 6 EndPoint supported
EndPoint 0 is control transfer
• 2 wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-
transfer or Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or Interrupt-
• 0 wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
transfer
EndPoint 1 to 5 comprise Double Buffer
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64bytes
• Endpoint 1: 256bytes
Cypress Semiconductor Corporation
Document Number: 002-04872 Rev. *E
• 198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 15, 2019