PRELIMINARY
CY8CLEDAC03
Figure 8. Soft Start of Chopping Operation
Chopping Operation
The chopping circuit provides two key functions:
■ Improves Power Factor
■ Enables dimmer compatibility
The chopping circuit is shown in Figure 7. When Q2 is driven with
short on pulses, the circuit operates as a boost converter. When
Q2 is on, the chopping inductor L3 stores energy. When Q2 is
off, this energy is released to capacitor C3 through diode D3.
Source resistor R6 is used to limit the current in the chopper path
to optimize efficiency of the circuit. A dithering algorithm controls
the switching period for Q2 to minimize EMI generated by the
mainly discontinuous operation of the boost circuit. During the
chopping period, the average current in L3 is in phase with and
proportional to the input mains voltage (voltage across ZVIN,
internal to the controller) resulting in high power factor.
Figure 7. Chopper Circuit
The chopper has six modes of operation as follows:
■ Leading Edge (LE) and Startup Leading Edge (SLE) modes:
Choppingis divided into normal and light. Thenormal chopping
period is adaptive. It is from leading edge to approximately
90-degree phase of line in every AC half-cycle (if 90-degree
phase of line is present). From 90-degree towards approxi-
mately post 160-degree phase the light chopping[1] is activated
to ensure accurate dimmer timing. Light chopping is disabled
if VIN voltage is greater than 1.5V to ensure accurate dimmer
timingwhenthephaseangleisaround90-degree. Thechopper
FET remains on through the zero-crossing point, until a little
beyond the leading edge in the next AC half-cycle (see
Figure 10)
■ Leading Edge Zero Phase Cut (LEZPC) mode: Chopping is
divided into normal and light. Normal chopping exists after
zero-crossing up to approximately 90-degree phase of line and
light chopping is activated towards approximately160-degree
phase. Light chopping will be blocked if VIN voltage is greater
than 1.5V. The chopper FET remains on through the
zero-crossing points for a fixed amount of time. (see left side
of Figure 9)
If the controller determines a dimmer is connected, Q2 is held on
when the input mains voltage is low. This provides a load on the
dimmer enabling the internal circuitry of the dimmer to reset
correctly every AC half-cycle. For leading edge dimmers, Q2 is
held on for a significant time after the TRIAC in the dimmer turns
on every AC half-cycle. During this period, R6 provides the load
necessary for the TRIAC latch current to be achieved. For trailing
edge dimmers, Q2 is held high just before the trailing edge. This
load forces the line to quickly fall to zero when the dimmer turns
off, enabling accurate detection of the dimmers on time. D8 and
D9 ensure C3 is charged to peak voltage output from the dimmer.
This maximizes the voltage on C3 each AC half-cycle,
minimizing the in rush current when the TRIAC fires on the next
AC half-cycle. At the start and end of every chopping period, “soft
start” and “soft stop” are incorporated to reduce power stress on
Q2 (see Figure 8)
■ Trailing Edge (TE) and Startup Trailing Edge (STE) modes:
Only normal chopping exists in this mode. Normal chopping is
activatedjustafterthezero-crossingofeveryAChalf-cycleand
continues until just before the trailing edge (see Figure 11). The
chopper FET turns on just before the trailing edge and
continues to the next AC half-cycle just after the zero-crossing
point. An overlap period[2] exists where the chopper FET turns
hard on just before the trailing edge. The overlap ensures
accurate dimmer timing. (see Figure 11).
■ Trailing Edge Zero Phase Cut (TEZPC) mode: Normal
chopping is seen across the entire AC half-cycle (see right side
of Figure 9)
Notes
1. The pulse width of ‘light chopping’ is 1/4 of normal chopping pulse width for CY8CLEDAC03L and 1/2 for CY8CLEDAC03H.
2. The length of ‘overlapping time’ is 90us for CY8CLEDAC03L and 112us for CY8CLEDAC03H.
Document Number: 001-68337 Rev *A
Page 9 of 22
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