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CY8C5588LTI-114 PDF预览

CY8C5588LTI-114

更新时间： 2024-01-29 21:52:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
102页 2766K
描述
Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLAINT, MO-220, QFN-68

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CY8C5588LTI-114 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLAINT, MO-220, QFN-68针数：68
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84地址总线宽度：
边界扫描：YES总线兼容性：USB
最大时钟频率：80 MHz外部数据总线宽度：
JESD-30 代码：S-XQCC-N68JESD-609代码：e4
长度：8 mm湿度敏感等级：3
I/O 线路数量：48端子数量：68
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC68,.32SQ,16封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.8/5 V认证状态：Not Qualified
RAM（字数）：32768ROM大小（位）：262144 Bits
座面最大高度：1 mm子类别：Other Microprocessor ICs
最大供电电压：5.5 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20紫外线可擦：N
宽度：8 mmBase Number Matches：1

CY8C5588LTI-114 数据手册

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PRELIMINARY  
PSoC® 5: CY8C55 Family Datasheet  
SWV. SWV output.  
3. Pin Descriptions  
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.  
May be used as a digital I/O pin; it is powered from VDDD instead  
of from a VDDIO. Pins are No Connect (NC) on devices without  
USB.[8]  
IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for  
high-current DACs (IDAC).  
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High  
current output of uncommitted opamp.[7]  
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.  
May be used as a digital I/O pin; it is powered from VDDD instead  
of from a VDDIO. Pins are No Connect (NC) on devices without  
USB.[8]  
Extref0, Extref1. External reference input to the analog system.  
OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to  
uncommitted opamp.  
VBOOST. Power sense connection to boost pump.  
VBAT. Battery supply to boost pump.  
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting  
input to uncommitted opamp.  
VCCA. Output of analog core regulator and input to analog core.  
Requires a 1 µF capacitor to VSSA. Regulator output not for  
external use.  
GPIO. Provides interfaces to the CPU, digital peripherals,  
analog peripherals, interrupts, LCD segment drive, and  
CapSense.[7]  
I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep  
on an address match. Any I/O pin can be used for I2C SCL if  
wake from sleep is not required.  
VCCD. Output of digital core regulator and input to digital core.  
The two VCCD pins must be shorted together, with the trace  
between them as short as possible, and a 1 µF capacitor to VSSD  
see Power System on page 20. Regulator output not for external  
use.  
;
I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep  
on an address match. Any I/O pin can be used for I2C SDA if  
wake from sleep is not required.  
VDDA. Supply for all analog peripherals and analog core  
regulator. VDDA must be the highest voltage present on the  
device. All other supply pins must be less than or equal to  
Ind. Inductor connection to boost pump.  
VDDA  
.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin.  
VDDD. Supply for all digital peripherals and digital core regulator.  
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33-MHz crystal oscillator  
pin.  
V
DDD must be less than or equal to VDDA  
.
VSSA. Ground for all analog peripherals.  
nTRST. Optional JTAG Test Reset programming and debug port  
connection to reset the JTAG connection.  
VSSB. Ground connection for boost pump.  
VSSD. Ground for all digital logic and I/O pins.  
SIO. Provides interfaces to the CPU, digital peripherals and  
interrupts with a programmable high threshold voltage, analog  
comparator, high sink current, and high impedance state when  
the device is unpowered.  
VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each  
VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V),  
and must be less than or equal to VDDA. If the I/O pins associated  
with VDDIO0, VDDIO2 or VDDIO3 are not used then that VDDIO  
should be tied to ground (VSSD or VSSA).  
SWDCK. SWD Clock programming and debug port connection.  
SWDIO. SWD Input and Output programming and debug port  
connection.  
XRES (and configurable XRES). External reset pin. Active low  
with internal pull-up. In 48-pin SSOP parts, P1[2] may be  
configured as XRES. In all other parts the pin is configured as a  
GPIO.  
TCK. JTAG Test Clock programming and debug port connection.  
TDI. JTAG Test Data In programming and debug port  
connection.  
TDO. JTAG Test Data Out programming and debug port  
connection.  
4. CPU  
4.1 ARM Cortex-M3 CPU  
TMS. JTAG Test Mode Select programming and debug port  
connection.  
The CY8C55 family of devices has an ARM Cortex-M3 CPU  
core. The Cortex-M3 is a low-power 32-bit three-stage pipelined  
Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is  
intended for deeply embedded applications that require fast  
interrupt handling features.  
TRACECLK. Cortex-M3 TRACEPORT connection, clocks  
TRACEDATA pins.  
TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections,  
output data.  
Notes  
7. GPIOs with opamp outputs are not recommended for use with CapSense.  
8. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.  
Document Number: 001-44094 Rev. *J  
Page 9 of 102  
[+] Feedback  
1...6789101112...102

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