PSoC® 4: PSoC 4200
Family Datasheet
Two Opamps (CTBm Block)
Figure 5. UDB Array
PSoC 4200 has two opamps with Comparator modes which
allow most common analog functions to be performed on-chip
eliminating external components; PGAs, voltage buffers, filters,
trans-impedance amplifiers, and other functions can be realized
with external passives saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive
the S/H circuit of the ADC without requiring external buffering.
System
Interconnect
CPU
Sub-system
Clocks
8
to 32
4
to 8
UDBIF
BUS IF IRQ IF CLK IF
Port IF
Port IF
Port IF
Temperature Sensor
DSI
DSI
PSoC 4200 has one on-chip temperature sensor This consists
of a diode, which is biased by a current source that can be
disabled to save power. The temperature sensor is connected to
the ADC, which digitizes the reading and produces a temper-
ature value using Cypress supplied software that includes
calibration and linearization.
UDB
UDB
Routing
Channels
Low-power Comparators
PSoC 4200 has a pair of low-power comparators, which can also
operate in the Deep Sleep and Hibernate modes. This allows the
analog system blocks to be disabled while retaining the ability to
monitor external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid metasta-
bility unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator switch event.
UDB
UDB
DSI
DSI
Programmable Digital Subsystem
UDBs can be clocked from a clock divider block, from a port
interface (required for peripherals such as SPI), and from the DSI
network directly or after synchronization.
Programmable Digital
Universal Digital Blocks (UDBs) and Port Interfaces
A port interface is defined, which acts as a register that can be
clocked with the same source as the PLDs inside the UDB array.
This allows faster operation because the inputs and outputs can
be registered at the port interface close to the I/O pins and at the
edge of the array. The port interface registers can be clocked by
one of the I/Os from the same port. This allows interfaces such
as SPI to operate at higher clock speeds by eliminating the delay
for the port input to be routed over DSI and used to register other
inputs (see Figure 6).
PSoC 4200 has four UDBs; the UDB array also provides a
switched Digital System Interconnect (DSI) fabric that allows
signals from peripherals and ports to be routed to and through
the UDBs for communication and control. The UDB array is
shown in the following figure.
The UDBs can generate interrupts (one UDB at a time) to the
interrupt controller. The UDBs retain the ability to connect to any
pin on the chip through the DSI.
Figure 6. Port Interface
High Speed I/O Matrix
To Clock
Tree
8
8
8
4
Input Registers
Output Registers
Enables
7
6
. . .
0
7
6
. . .
0
3
2
1
0
Digital
GlobalClocks
9
4
[1]
[0]
[1]
Clock Selector
Block from
UDB
2
2
3 DSI Signals ,
1 I/O Signal
4
8
8
[1]
[0]
[1]
Reset Selector
Block from
UDB
From DSI
To DSI
From DSI
Document Number: 001-87197 Rev. *J
Page 7 of 45
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