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CY8C4146AXI-S455 PDF预览

CY8C4146AXI-S455

更新时间: 2023-09-03 20:26:18
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英飞凌 - INFINEON /
页数 文件大小 规格书
54页 852K
描述
32位PSoC™ 4 Arm® Cortex®-M0/M0+

CY8C4146AXI-S455 数据手册

 浏览型号CY8C4146AXI-S455的Datasheet PDF文件第2页浏览型号CY8C4146AXI-S455的Datasheet PDF文件第3页浏览型号CY8C4146AXI-S455的Datasheet PDF文件第4页浏览型号CY8C4146AXI-S455的Datasheet PDF文件第5页浏览型号CY8C4146AXI-S455的Datasheet PDF文件第6页浏览型号CY8C4146AXI-S455的Datasheet PDF文件第7页 
CY8C41xx  
PSoC™ 4 MCU: PSoC™ 4100S Plus  
Based on Arm® Cortex®-M0+ CPU  
General description  
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system  
controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital  
blocks with flexible automatic routing. PSoC™ 4100S Plus is a member of the PSoC™ 4 platform architecture. It is  
a combination of a microcontroller with standard communication and timing peripherals, a capacitive  
touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose  
continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4100S Plus  
products are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.  
Features  
• 32-bit MCU subsystem  
- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply  
- Up to 128 KB of flash with read accelerator  
- Up to 16 KB of SRAM  
- 8-channel DMA engine  
• Programmable analog  
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and comparator  
modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.  
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averag-  
ing  
- Single-slope 10-bit ADC function provided by a capacitance sensing block  
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin  
- Two low-power comparators that operate in Deep Sleep low-power mode  
• Programmable digital  
- Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs  
• Low-power 1.71-V to 5.5-V operation  
- Deep Sleep mode with operational analog and 2.5-µA digital system current  
• Capacitive sensing  
- Capacitive sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance  
- Infineon-supplied software component makes capacitive sensing design easy  
- Automatic hardware tuning (SmartSense)  
• LCD drive capability  
- LCD segment drive capability on GPIOs  
• Serial communication  
- Five independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI,  
or UART functionality  
• Timing and pulse-width modulation  
- Eight 16-bit Timer, Counter, Pulse-Width Modulator (TCPWM) blocks  
- Center-aligned, edge, and pseudo-random modes  
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications  
- Quadrature decoder  
Datasheet  
www.infineon.com  
Please read the Important Notice and Warnings at the end of this document  
page 1  
002-19966 Rev. *K  
2023-01-24  

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