PSoC® 4: PSoC 4XX8 BLE 4.2
Family Datasheet
PRELIMINARY
Programmable System-on-Chip (PSoC®)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4XX8 BLE 4.2 product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low
Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic,
high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard communication and timing
peripherals. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Subsystem
Capacitive Sensing
■ 48-MHz ARM Cortex-M0 CPU with single-cycle multiply and
DMA
■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and liquid tolerance
■ Up to 256 KB of flash with Read Accelerator
■ Up to 32 KB of SRAM
■ Cypress-supplied software component makes capacitive
sensing design easy
■ Automatic hardware tuning algorithm (SmartSense™)
BLE Radio and Subsystem
■ BLE 4.2 support
Segment LCD Drive
■ LCD drive supported on all pins (common or segment)
■ Operates in Deep Sleep mode with four bits per pin memory
■ 2.4-GHz RF transceiver with 50-Ω antenna drive
■ Digital PHY
Serial Communication
■ Link-Layer engine supporting master and slave modes
■ RF output power: –18 dBm to +3 dBm
■ RX sensitivity: –92 dBm
■ Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
■ RX current: 18.7 mA
Timing and Pulse-Width Modulation
■ TX current: 16.5 mA at 0 dBm
■ RSSI: 1-dB resolution
■ Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Programmable Analog
■ Center-aligned, Edge, and Pseudo-random modes
■ Four opamps with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator modes, and ADC
input buffering capability. Can operate in Deep Sleep mode.
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 36 Programmable GPIOs
■ 7 mm × 7 mm 56-pin QFN package
■ 76-ball CSP package
■ 12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■ Any GPIO pin can be CapSense, LCD, analog, or digital
■ Two low-power comparators that operate in Deep Sleep mode
■ Two overvoltage-tolerant (OVT) pins; drive modes, strengths,
and slew rates are programmable
Programmable Digital
PSoC Creator™ Design Environment
■ Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and data path
■ Integrated Design Environment (IDE) provides schematic
design entry and build (with analog and digital automatic
routing)
■ Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
■ API components for all fixed-function and programmable
peripherals
Power Management
■ Active mode: 1.7 mA at 3-MHz flash program execution
Industry-Standard Tool Compatibility
■ Deep Sleep mode: 1.5 µA with watch crystal oscillator (WCO)
on
■ After schematic entry, development can be done with
ARM-based industry-standard development tools
■ Hibernate mode: 150 nA with RAM retention
■ Stop mode: 60 nA
Cypress Semiconductor Corporation
Document Number: 002-09848 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 9, 2016
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