CY8C41xx-BL
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE product
family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth® Low Energy,
also known as Bluetooth® Smart, radio and subsystem (BLESS), compliant with Bluetooth® 4.2 specifications.
The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC),
opamps with comparator mode, and standard communication and timing peripherals. The PSoC™ 4
CY8C41xx-BL MCU with AIROC™ Bluetooth® LE products will be fully upward compatible with members of the
PSoC™ 4 platform for new applications and design needs. The programmable analog and digital subsystems
allow flexibility and in-field tuning of the design.
Features
• 32-bit MCU subsystem
- 24-MHz Arm® Cortex®-M0 CPU with single-cycle multiply
- Up to 256 KB of flash with read accelerator
- Up to 32 KB of SRAM
• Bluetooth® LE radio and subsystem
- 2.4-GHz RF transceiver with Bluetooth® LE 4.2 support and 50-Ω antenna drive
- Digital PHY
- Link layer engine supporting master and slave modes
- RF output power: –18 dBm to +3 dBm
- RX sensitivity: –89 dBm
- RX current: 16.4 mA
- TX current: 15.6 mA at 0 dBm
- Received Signal Strength Indication (RSSI): 1-dB resolution
• Programmable analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes,
and ADC input buffering capability; can operate in Deep-Sleep mode.
- 12-bit, 806 ksps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep-Sleep mode
• Power management
- Active mode: 1.7 mA at 3-MHz flash program execution
- Deep-Sleep mode: 1.3 µA with watch crystal oscillator (WCO) on
- Hibernate mode: 150 nA with RAM retention
- Stop mode: 60 nA
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance
- Infineon-supplied software component makes capacitive-sensing design easy
- Automatic hardware-tuning algorithm (SmartSense)
• Segment LCD drive
- LCD drive supported on all pins (common or segment)
- Operates in Deep-Sleep mode with four bits per pin memory
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
002-23052 Rev. *B
2023-03-29
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