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CY8C27543-24AIT

更新时间： 2024-11-18 22:35:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
44页	543K
描述
PSoC Mixed Signal Array

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技术参数
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CY8C27543-24AIT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LEAD FREE, PLASTIC, MS-026, TQFP-44
针数：	44	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.24
其他特性：	ALSO OPERATES AT 3.3V SUPPLY	地址总线宽度：
位大小：	8	边界扫描：	NO
CPU系列：	M8C	最大时钟频率：	24 MHz
外部数据总线宽度：		JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e0	长度：	10 mm
I/O 线路数量：	40	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP44,.47SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	电源：	3.3/5 V
认证状态：	Not Qualified	RAM（字节）：	256
RAM（字数）：	256	ROM（单词）：	16384
ROM可编程性：	FLASH	座面最大高度：	1.6 mm
速度：	24 MHz	子类别：	Microcontrollers
最大压摆率：	8 mA	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

CY8C27543-24AIT 数据手册

PSoC™ Mixed Signal Array

Final Data Sheet

CY8C27143, CY8C27243,

CY8C27443, CY8C27543, and CY8C27643

Features

■ Powerful Harvard Architecture Processor

■ M8C Processor Speeds to 24 MHz

■ 8x8 Multiply, 32-Bit Accumulate

■ Low Power at High Speed

■ Precision, Programmable Clocking

■ Internal 2.5% 24/48 MHz Oscillator

■ Additional System Resources

■ I²C™ Slave, Master, and Multi-Master to

■ 24/48 MHz with Optional 32 kHz Crystal

■ Optional External Oscillator, up to 24 MHz

■ Internal Oscillator for Watchdog and Sleep

400 kHz

■ Watchdog and Sleep Timers

■ User-Configurable Low Voltage Detection

■ Integrated Supervisory Circuit

■ On-Chip Precision Voltage Reference

■ 3.0 to 5.25 V Operating Voltage

■ Operating Voltages Down to 1.0V Using On-

■ Flexible On-Chip Memory

Chip Switch Mode Pump (SMP)

■ 16K Bytes Flash Program Storage 50,000

■ Industrial Temperature Range: -40°C to +85°C

Erase/Write Cycles

■ Complete Development Tools

■ Advanced Peripherals (PSoC Blocks)

■ 256 Bytes SRAM Data Storage

■ In-System Serial Programming (ISSP™)

■ Partial Flash Updates

■ Flexible Protection Modes

■ EEPROM Emulation in Flash

■ Free Development Software

■ 12 Rail-to-Rail Analog PSoC Blocks Provide:

(PSoC™ Designer)

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

■ 8 Digital PSoC Blocks Provide:

■ Full-Featured, In-Circuit Emulator and

Programmer

■ Full Speed Emulation

■ Complex Breakpoint Structure

■ 128K Bytes Trace Memory

■ Programmable Pin Configurations

■ 25 mA Sink on all GPIO

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Up to 2 Full-Duplex UARTs

- Multiple SPI™ Masters or Slaves

- Connectable to all GPIO Pins

■ Pull up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

■ Up to 12 Analog Inputs on GPIO

■ Four 30 mA Analog Outputs on GPIO

■ Configurable Interrupt on all GPIO

■ Complex Peripherals by Combining Blocks

Analog

Drivers

PSoC™ Functional Overview

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

PSoC

CORE

The PSoC™ family consists of many Mixed Signal Array with

On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components

with one, low cost single-chip programmable device. PSoC

devices include configurable blocks of analog and digital logic,

as well as programmable interconnects. This architecture

allows the user to create customized peripheral configurations

that match the requirements of each individual application.

Additionally, a fast CPU, Flash program memory, SRAM data

memory, and configurable IO are included in a range of conve-

nient pinouts and packages.

System Bus

Global Digital Interconnect

SRAM

Global Analog Interconnect

SROM

Flash 16K

256 Bytes

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

Controller

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: PSoC Core, Digital System, Analog System,

and System Resources. Configurable global busing allows all

the device resources to be combined into a complete custom

system. The PSoC CY8C27x43 family can have up to five IO

ports that connect to the global digital and analog interconnects,

providing access to 8 digital blocks and 12 analog blocks.

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref

Digital

Block

Array

Analog

Block

Array

(2 Rows,

8 Blocks)

(4 Columns,

12 Blocks)

Analog

Input

Muxing

The PSoC Core

The PSoC Core is a powerful engine that supports a rich fea-

ture set. The core includes a CPU, memory, clocks, and config-

urable GPIO (General Purpose IO).

POR and LVD Internal

Voltage

Switch

Mode

Pump

Digital

Clocks Accum.

Multiply

I²C

Decimator

System Resets

Ref.

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four MIPS 8-bit Harvard architecture micro-

SYSTEM RESOURCES

August 3, 2004

12 3 4 5 6 7...44

中文翻译

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与CY8C27543-24AIT相关器件

型号	品牌	获取价格	描述	数据表
CY8C27543-24AXI	CYPRESS	获取价格	PSoC Mixed Signal Array
CY8C27543-24AXI	INFINEON	获取价格	CY8C27x43
CY8C27543-24AXIT	CYPRESS	获取价格	PSoC Mixed Signal Array
CY8C27566	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-24AXI	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-24AXIT	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPAXC	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPAXE	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPAXI	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPLFXC	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array

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