Datasheet > CY8C27566-24AXI

CY8C27566-24AXI

更新时间： 2024-11-19 03:55:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
39页	799K
描述
PSoC⑩ Mixed Signal Array

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技术参数
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CY8C27566-24AXI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LEAD FREE, TQFP-44	针数：	44
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	地址总线宽度：
位大小：	8	边界扫描：	NO
CPU系列：	M8C	最大时钟频率：	24 MHz
外部数据总线宽度：		JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e4	长度：	10 mm
湿度敏感等级：	3	I/O 线路数量：	40
端子数量：	44	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP44,.47SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	260	电源：	3.3,5 V
认证状态：	Not Qualified	RAM（字节）：	1024
RAM（字数）：	1024	ROM（单词）：	32768
ROM可编程性：	FLASH	座面最大高度：	1.8 mm
速度：	24 MHz	子类别：	Microcontrollers
最大压摆率：	14 mA	最大供电电压：	5.25 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	10 mm	Base Number Matches：	1

CY8C27566-24AXI 数据手册

PSoC™ Mixed Signal Array

CY8C27466, CY8C27566, and CY8C27666

Features

Preliminary Data Sheet

■

Powerful Harvard Architecture Processor

■

Precision, Programmable Clocking

■ Additional System Resources

❐

M8C Processor Speeds to 24 MHz

Two 8x8 Multiply, 32-Bit Accumulate

Low Power at High Speed

3.0 to 5.25 V Operating Voltage

Operating Voltages Down to 1.0V Using On-

Chip Switch Mode Pump (SMP)

❐

Internal ±2.5% 24/48 MHz Oscillator

❐

I²C Slave, Master, and Multi-Master to

400 kHz

Watchdog and Sleep Timers

User-Configurable Low Voltage Detection

Integrated Supervisory Circuit

On-Chip Precision Voltage Reference

24/48 MHz with Optional 32.768 kHz Crystal

Optional External Oscillator, up to 24 MHz

Internal Oscillator for Watchdog and Sleep

❐

■

Flexible On-Chip Memory

❐

32K Bytes Flash Program Storage 50,000

Erase/Write Cycles

1K Bytes SRAM Data Storage

In-System Serial Programming (ISSP)

Partial Flash Updates

❐

Industrial Temperature Range: -40°C to +85°C

■

Complete Development Tools

❐

■

Advanced Peripherals (PSoC Blocks)

❐

Free Development Software

(PSoC™ Designer)

Full-Featured, In-Circuit Emulator and

Programmer

12 Rail-to-Rail Analog PSoC Blocks Provide:

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

❐

Flexible Protection Modes

EEPROM Emulation in Flash

❐

Full Speed Emulation

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

8 Digital PSoC Blocks Provide:

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Up to 2 Full-Duplex UARTs

- Multiple SPI Masters or Slaves

- Connectable to all GPIO Pins

Complex Breakpoint Structure

128K Bytes Trace Memory

Complex Events

■

Programmable Pin Configurations

❐

25 mA Sink on all GPIO

Pull up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

Up to 12 Analog Inputs on GPIO

Four 40 mA Analog Outputs on GPIO

Configurable Interrupt on all GPIO

C Compilers, Assembler, and Linker

❐

Complex Peripherals by Combining Blocks

Analog

Drivers

PSoC™ Functional Overview

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

PSoC

CORE

The PSoC™ family consists of many Mixed Signal Array with

On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components

with one, low cost single-chip programmable device. PSoC

devices include configurable blocks of analog and digital logic,

as well as programmable interconnects. This architecture

allows the user to create customized peripheral configurations

that match the requirements of each individual application.

Additionally, a fast CPU, Flash program memory, SRAM data

memory, and configurable IO are included in a range of conve-

nient pinouts and packages.

SYSTEM BUS

Global Digital Interconnect

SRAM

Global Analog Interconnect

SROM

Flash 32K

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

Controller

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: PSoC Core, Digital System, Analog System,

and System Resources. Configurable global busing allows all

the device resources to be combined into a complete custom

system. The PSoC CY8C27x66 family can have up to five IO

ports that connect to the global digital and analog interconnects,

providing access to 16 digital blocks and 12 analog blocks.

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref

Analog

Block

Array

Digital

Block Array

(2 Rows,

8 Blocks)

(4 Columns,

12 Blocks)

Analog

Input

Muxing

The PSoC Core

The PSoC Core is a powerful engine that supports a rich fea-

ture set. The core includes a CPU, memory, clocks, and config-

urable GPIO (General Purpose IO).

Two

POR and LVD Internal

Voltage

Switch

Mode

Pump

Digital

Clocks

I²C

Multiply Decimator

Accum.

System Resets

Ref.

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four MIPS 8-bit Harvard architecture micro-

processor. The CPU utilizes an interrupt controller with 18 vec-

SYSTEM RESOURCES

June 2004

12 3 4 5 6 7...39

中文翻译

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与CY8C27566-24AXI相关器件

型号	品牌	获取价格	描述	数据表
CY8C27566-24AXIT	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPAXC	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPAXE	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPAXI	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPLFXC	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPLFXE	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPLFXI	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPPVXC	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPPVXE	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array
CY8C27566-SPPVXI	CYPRESS	获取价格	PSoC⑩ Mixed Signal Array

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