PSoC™ Mixed Signal Array
CY8C27466, CY8C27566, and CY8C27666
Features
Preliminary Data Sheet
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Powerful Harvard Architecture Processor
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Precision, Programmable Clocking
■ Additional System Resources
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M8C Processor Speeds to 24 MHz
Two 8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0 to 5.25 V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
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Internal ±2.5% 24/48 MHz Oscillator
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I2C Slave, Master, and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
24/48 MHz with Optional 32.768 kHz Crystal
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
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Flexible On-Chip Memory
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32K Bytes Flash Program Storage 50,000
Erase/Write Cycles
1K Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
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Industrial Temperature Range: -40°C to +85°C
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Complete Development Tools
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Advanced Peripherals (PSoC Blocks)
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Free Development Software
(PSoC™ Designer)
Full-Featured, In-Circuit Emulator and
Programmer
12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
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Flexible Protection Modes
EEPROM Emulation in Flash
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Full Speed Emulation
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
8 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI Masters or Slaves
- Connectable to all GPIO Pins
Complex Breakpoint Structure
128K Bytes Trace Memory
Complex Events
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Programmable Pin Configurations
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25 mA Sink on all GPIO
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 12 Analog Inputs on GPIO
Four 40 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
C Compilers, Assembler, and Linker
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Complex Peripherals by Combining Blocks
Analog
Drivers
PSoC™ Functional Overview
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
SYSTEM BUS
Global Digital Interconnect
SRAM
Global Analog Interconnect
SROM
Flash 32K
1K
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x66 family can have up to five IO
ports that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Analog
Block
Array
Digital
Block Array
(2 Rows,
8 Blocks)
(4 Columns,
12 Blocks)
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
Two
POR and LVD Internal
Voltage
Switch
Mode
Pump
Digital
Clocks
I2C
Multiply Decimator
Accum.
System Resets
Ref.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU utilizes an interrupt controller with 18 vec-
SYSTEM RESOURCES
June 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12019 Rev. *B
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