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CY8C24423A-12PVXE PDF预览

CY8C24423A-12PVXE

更新时间: 2024-11-24 04:53:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
33页 455K
描述
PSoC㈢ Mixed-Signal Array

CY8C24423A-12PVXE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP28,.3针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:1 week
风险等级:5.75地址总线宽度:
位大小:8边界扫描:NO
CPU系列:M8C最大时钟频率:24.96 MHz
外部数据总线宽度:JESD-30 代码:R-PDSO-G28
JESD-609代码:e4长度:10.2 mm
湿度敏感等级:3I/O 线路数量:24
端子数量:28最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not QualifiedRAM(字节):256
RAM(字数):256ROM(单词):4096
ROM可编程性:FLASH座面最大高度:2 mm
速度:12 MHz子类别:Microcontrollers
最大压摆率:8 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mm

CY8C24423A-12PVXE 数据手册

 浏览型号CY8C24423A-12PVXE的Datasheet PDF文件第2页浏览型号CY8C24423A-12PVXE的Datasheet PDF文件第3页浏览型号CY8C24423A-12PVXE的Datasheet PDF文件第4页浏览型号CY8C24423A-12PVXE的Datasheet PDF文件第5页浏览型号CY8C24423A-12PVXE的Datasheet PDF文件第6页浏览型号CY8C24423A-12PVXE的Datasheet PDF文件第7页 
PSoC® Mixed-Signal Array  
Final Data Sheet  
Automotive:  
CY8C24223A and CY8C24423A  
Features  
Powerful Harvard Architecture Processor  
Precision, Programmable Clocking  
Additional System Resources  
2
M8C Processor Speeds to 12 MHz  
8x8 Multiply, 32-Bit Accumulate  
Low Power at High Speed  
4.75V to 5.25V Operating Voltage  
Extended Temp. Range: -40°C to +125°C  
Internal ±4% 24 MHz Oscillator  
High-Accuracy 24 MHz with Optional 32 kHz  
Crystal and PLL  
I CSlave, Master, and Multi-Master to  
400 kHz  
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
On-Chip Precision Voltage Reference  
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
Flexible On-Chip Memory  
Advanced Peripherals (PSoC Blocks)  
4K Bytes Flash Program Storage 100 Erase/  
Write Cycles  
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
6 Rail-to-Rail Analog PSoC Blocks Provide:  
- Up to 14-Bit ADCs  
- Up to 9-Bit DACs  
- Programmable Gain Amplifiers  
- Programmable Filters and Comparators  
4 Digital PSoC Blocks Provide:  
- 8- to 32-Bit Timers, Counters, and PWMs  
- CRC and PRS Modules  
Complete Development Tools  
Free Development Software  
(PSoC Designer™)  
Full-Featured, In-Circuit Emulator and  
Programmer  
Flexible Protection Modes  
Full Speed Emulation  
Complex Breakpoint Structure  
128K Bytes Trace Memory  
Programmable Pin Configurations  
25 mA Sink on All GPIO  
Pull Up, Pull Down, High Z, Strong, or Open  
Drain Drive Modes on All GPIO  
Up to 10 Analog Inputs on GPIO  
Two 30 mA Analog Outputs on GPIO  
Configurable Interrupt on All GPIO  
- Full-Duplex UART  
- Multiple SPIMasters or Slaves  
- Connectable to all GPIO Pins  
Complex Peripherals by Combining Blocks  
Analog  
Drivers  
PSoC® Functional Overview  
Port 2 Port 1 Port 0  
PSoC CORE  
The PSoC® family consists of many Mixed-Signal Array with  
On-Chip Controller devices. These devices are designed to  
replace multiple traditional MCU-based system components  
with one, low cost single-chip programmable device. PSoC  
devices include configurable blocks of analog and digital logic,  
as well as programmable interconnects. This architecture  
allows the user to create customized peripheral configurations  
that match the requirements of each individual application.  
Additionally, a fast CPU, Flash program memory, SRAM data  
memory, and configurable IO are included in a range of conve-  
nient pinouts and packages.  
System Bus  
Global Digital Interconnect  
SRAM  
Global Analog Interconnect  
Flash 4K  
SROM  
256 Bytes  
Sleep and  
Watchdog  
CPUCore(M8C)  
Interrupt  
Controller  
Multiple Clock Sources  
(IncludesIMO,ILO,PLL,andECO)  
The PSoC architecture, as illustrated on the left, is comprised of  
four main areas: PSoC Core, Digital System, Analog System,  
and System Resources. Configurable global busing allows all  
the device resources to be combined into a complete custom  
system. The PSoC automotive CY8C24x23A group can have  
up to three IO ports that connect to the global digital and analog  
interconnects, providing access to 4 digital blocks and 6 analog  
blocks.  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
Analog  
Block  
Array  
Digital  
Block Array  
(1 Row,  
4 Blocks)  
(2 Columns,  
6 Blocks)  
Analog  
Input  
Muxing  
The PSoC Core  
The PSoC Core is a powerful engine that supports a rich fea-  
ture set. The core includes a CPU, memory, clocks, and config-  
urable GPIO (General Purpose IO).  
POR and LVD  
System Resets  
Internal  
Voltage  
Ref.  
Digital  
Clocks  
Multiply  
Accum .  
I2C  
Decimator  
SYSTEM RESOURCES  
October 9, 2006  
© Cypress Semiconductor Corp. 2004-2006 — Document No. 38-12029 Rev. *C  
1
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