Datasheet > CY8C20667S-24LQXI

CY8C20667S-24LQXI

更新时间： 2023-12-06 20:12:52

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
46页	1181K
描述
CY8C20xx7/S

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CY8C20667S-24LQXI 数据手册

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CY8C20xx7/S

Pinouts

The CY8C20x37/47/67/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables.

Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, V_SS, V_DD, and XRES

are not capable of digital I/O.

16-pin SOIC (10 Sensing Inputs)

Table 1. Pin Definitions – CY8C20237-24SXI, CY8C20247/S-24SXI ^[3]

Type

Figure 2. CY8C20237-24SXI, CY8C20247/S-24SXI

Device

No.

Name

Description

Digital Analog

I/O

P0[3] Integrating Input

P0[1] Integrating Input

P2[5] Crystal output (XOut)

P2[3] Crystal input (XIn)

P1[7] I2C SCL, SPI SS

P1[5] I2C SDA, SPI MISO

P1[3]

AI, P0[3]

P0[7], AI

AI, P0[1]

AI, P2[5]

V_DD

P0[4], AI

AI, P2[3]

AI, P1[7]

XRES

P1[4], EXTCLK

SOIC

AI, P1[5]

AI, P1[3]

P1[2], AI

P1[0], ISSP DATA, I²C SDA, SPI CLK, AI

AI, ISSP CLK, I²C SCL, SPI MOSI, P1[1]

V_SS

P1[1] ISSP CLK^[4], I²C SCL, SPI

MOSI

Power

V_SSGround connection^[7]

I/O

P1[0] ISSP DATA^[4], I²C SDA, SPI

CLK^[5]

I/O

P1[2] Driven Shield Output (optional)

P1[4] Optional external clock

(EXTCLK)

INPUT

Power

XRES Active high external reset with

internal pull-down^[6]

I/O

P0[4]

V_DDSupply voltage

P0[7]

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Notes

3. 13 GPIOs = 10 pins for capacitive sensing+2 pins for I²C + 1 pin for modulator capacitor.

4. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance

(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.

5. Alternate SPI clock.

6. The internal pull down is 5KOhm.

7. All VSS pins should be brought out to one common GND plane.

Document Number: 001-69257 Rev. *Q

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