Datasheet > CY7C451-12JI

CY7C451-12JI

更新时间： 2024-11-24 04:53:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片时钟
页数	文件大小	规格书
24页	354K
描述
512x9 2Kx9 and 4Kx9 Cascadable Clocked FIFOs with Programmable

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CY7C451-12JI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFJ	包装说明：	PLASTIC, LCC-32
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.85	最长访问时间：	9 ns
其他特性：	RETRANSMIT	最大时钟频率 (fCLK)：	83.3 MHz
周期时间：	12 ns	JESD-30 代码：	R-PQCC-J32
JESD-609代码：	e0	长度：	13.97 mm
内存密度：	4608 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	9	功能数量：	1
端子数量：	32	字数：	512 words
字数代码：	512	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512X9	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC32,.5X.6
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	3.55 mm	最大待机电流：	0.03 A
子类别：	FIFOs	最大压摆率：	0.15 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	11.43 mm
Base Number Matches：	1

CY7C451-12JI 数据手册

CY7C451

CY7C453

CY7C454

512x9, 2Kx9, and 4Kx9 Cascadable

Clocked FIFOs with Programmable

and write interfaces. Both FIFOs are 9 bits wide. The

CY7C451 has a 512-word by 9-bit memory array, the

CY7C453 has a 2048-word by 9-bit memory array, and the

CY7C454 has a 4096-word by 9-bit memory array. Devices

can be cascaded to increase FIFO depth. Programmable fea-

tures include Almost Full/Empty flags and generation/checking

of parity. These FIFOs provide solutions for a wide variety of data

buffering needs, including high-speed data acquisition, multiproces-

sor interfaces, and communications buffering.

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

• 512 x 9 (CY7C451)

• 2,048 x 9 (CY7C453)

• 4,096 x 9 (CY7C454)

• 0.65 micron CMOS for optimum speed/power

• High-speed 83-MHz operation (12 ns read/write cycle

time)

Both FIFOs have 9-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (CKW) and a write enable

pin (ENW). When ENW is asserted, data is written into the FIFO on

the rising edge of the CKW signal. While ENW is held active, data is

continually written into the FIFO on each CKW cycle. The output port

is controlled in a similar manner by a free-running read clock (CKR)

and a read enable pin (ENR). The read (CKR) and write (CKW)

clocks may be tied together for single-clock operation or the two

clocks may be run independently for asynchronous read/write appli-

cations. Clock frequencies up to 83.3 MHz are achievable in the stan-

dalone configuration, and up to 83.3 MHz is achievable when FIFOs

are cascaded for depth expansion.

• Low power — I_CC=70 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, HalfFull, andprogrammableAlmostEmpty

and Almost Full status flags

• TTL compatible

• Retransmit function

• Parity generation/checking

• Output Enable (OE) pins

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

Depth expansion is possible using the cascade input (XI) and

cascade output (XO). The XOsignal is connected to the XI of the next

device, and the XO of the last device should be connected to the XI

of the first device. In standalone mode, the input (XI) pin is simply tied

• Depth Expansion Capability

• Available in PLCC packages

to V_SS

In the standalone and width expansion configurations, a LOW

on the retransmit (RT) input causes the FIFOs to retransmit

the data. Read enable (ENR) and the write enable (ENW) must

both be HIGH during the retransmit, and then ENR is used to

access the data.

Functional Description

The CY7C451, CY7C453, and CY7C454 are high-speed,

low-power, first-in first-out (FIFO) memories with clocked read

0– 8

Logic Block Diagram

Pin Configurations

INPUT

PLCC/LCC

Top View

CKW

ENW

D D D D D

2 3 4 5 6

FLAG/PARITY

PROGRAM

1 32 31 30

PARITY

ENW

CKW

FL/RT

WRITE

CONTROL

7C451

7C453

7C454

E/F

PAFE/XO

FLAG

LOGIC

E/F

CKR

ENR

RAM

ARRAY

512x9

2048x9

4096x9

PAFE/XO

READ

POINTER

WRITE

POINTER

/PG/PE

14 15 16 17 1819 20

Q Q Q Q Q Q Q

C451-2

RESET

LOGIC

FL/RT

TRI–STATE

OUTPUT REGISTER

READ

CONTROL

EXPANSION

LOGIC

RETRANSMIT

LOGIC

Q /PG/PE

CKR

ENR

C451-1

0–7,

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06033 Rev. *A

Revised December 27, 2002

12 3 4 5 6 7...24

中文翻译

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与CY7C451-12JI相关器件

型号	品牌	获取价格	描述	数据表
CY7C451-12JIR	CYPRESS	获取价格	FIFO, 512X9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C451-12JIT	CYPRESS	获取价格	FIFO, 512X9, 9ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C451-14DI	ETC	获取价格	x9 Synchronous FIFO
CY7C451-14DMB	CYPRESS	获取价格	FIFO, 512X9, 10ns, Synchronous, CMOS, CDIP32, 0.300 INCH, CERDIP-32
CY7C451-14JC	CYPRESS	获取价格	512x9 2Kx9 and 4Kx9 Cascadable Clocked FIFOs with Programmable
CY7C451-14JC	ROCHESTER	获取价格	512X9 OTHER FIFO, 10ns, PQCC32, PLASTIC, LCC-32
CY7C451-14JCR	CYPRESS	获取价格	暂无描述
CY7C451-14JCT	CYPRESS	获取价格	FIFO, 512X9, 10ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C451-14JI	CYPRESS	获取价格	512x9 2Kx9 and 4Kx9 Cascadable Clocked FIFOs with Programmable
CY7C451-14JIR	CYPRESS	获取价格	FIFO, 512X9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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