Datasheet > CY7C43643V-15AC

CY7C43643V-15AC

更新时间： 2024-02-06 08:02:18

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
27页	554K
描述
FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128

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CY7C43643V-15AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
针数：	128	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.69	Is Samacsys：	N
最长访问时间：	10 ns	其他特性：	MAIL BOX; RETRANSMIT
最大时钟频率 (fCLK)：	67 MHz	周期时间：	15 ns
JESD-30 代码：	R-PQFP-G128	JESD-609代码：	e0
长度：	20 mm	内存密度：	36864 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	36
功能数量：	1	端子数量：	128
字数：	1024 words	字数代码：	1000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1KX36
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP128,.63X.87,20
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.012 A
子类别：	FIFOs	最大压摆率：	0.06 mA
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

CY7C43643V-15AC 数据手册

CY7C43643V

CY7C43663V/CY7C43683V

PRELIMINARY

Pin Definitions

Signal Name

Description

I/O

Function

Port A Data

I/O 36-bit Unidirectional data port for side A.

0–35

Almost Empty

Flag (Port B)

Programmable almost-empty flag synchronized to CLKA. It is LOW when the number

of words in the FIFO2 is less than or equal to the value in the almost-empty A offset

Almost Full Flag

Port B Data

Programmable almost-full flag synchronized to CLKA. It is LOW when the number of

empty locations in the FIFO is less than or equal to the value in the almost-full A offset

I/O 36-bit Unidirectional data port for side B.

0–35

BE/FWFT

Big Endian/First

Word Fall

Through Select

This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian

operation. In this case, depending on the bus size, the most significant byte or word on

Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data

flow). A LOW on BE will select Little Endian operation. In this case, the least significant

byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port

B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH

on FWFT selects CY Standard mode, a LOW selects First Word Fall Through mode.

Once the timing mode has been selected, the level on FWFT must be static throughout

device operation.

Bus Match

Select (Port B)

A HIGH on this pin enables either byte or word bus width on Port B, depending on the

state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to

select the bus size and endian arrangement for Port B. The level of BM must be static

throughout device operation.

CLKA

CLKB

Port A Clock

Port B Clock

CLKA is a continuous clock that synchronizes all data transfers through Port A and can

be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the

LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through Port B and can

be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all synchro-

nized to the LOW-to-HIGH transition of CLKB.

CSA

Port A Chip

Select

CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on

Port A. The A

outputs are in the high-impedance state when CSA is HIGH.

0–35

CSB

Port B Chip

Select

CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on

Port B. The B outputs are in the high-impedance state when CSB is HIGH.

0–35

EF/OR

Empty/Output

Ready Flag

(Port B)

This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF

indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function

is selected. OR indicates the presence of valid data on A

outputs, available for

0–35

reading. FF/OR is synchronized to the LOW-to-HIGH transition of CLKB.

ENA

ENB

FF/IR

Port A Enable

Port B Enable

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data

on Port A.

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data

on Port B.

Port B Full/Input

Ready Flag

This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF

indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function

is selected. IR indicates whether or not there is space available for writing to the FIFO

memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.

FS1/SEN

FS0/SD

Flag Offset

Select 1/Serial

Enable

FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-

ming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag

offset programming method. Three offset register programming methods are available:

automatically load one of three preset values (8, 16, or 64), parallel load from Port A,

and serial load. When serial load is selected for flag offset register programming,

FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.

When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into

the X and Y registers. The number of bit writes required to program the offset registers

is 40 for the CY7C43643, 48 for the CY7C43663, and 56 for the CY7C43683. The first

bit write stores the Y-register MSB and the last bit write stores the X-register LSB.

Flag Offset

Select 0/Serial

Data

1 2 345 6 7...27

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