Datasheet > CY7C43643V-15AC

CY7C43643V-15AC

更新时间： 2024-01-02 07:10:45

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
27页	554K
描述
FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128

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CY7C43643V-15AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
针数：	128	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.69	Is Samacsys：	N
最长访问时间：	10 ns	其他特性：	MAIL BOX; RETRANSMIT
最大时钟频率 (fCLK)：	67 MHz	周期时间：	15 ns
JESD-30 代码：	R-PQFP-G128	JESD-609代码：	e0
长度：	20 mm	内存密度：	36864 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	36
功能数量：	1	端子数量：	128
字数：	1024 words	字数代码：	1000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1KX36
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP128,.63X.87,20
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.012 A
子类别：	FIFOs	最大压摆率：	0.06 mA
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

CY7C43643V-15AC 数据手册

CY7C43643V

CY7C43663V/CY7C43683V

PRELIMINARY

access that word (along with all other words residing in mem-

ory). In the First Word Fall Through Mode (FWFT), the first

long-word (36-bit wide) written to an empty FIFO appears au-

tomatically on the outputs, no read operation required (never-

theless, accessing subsequent words does necessitate a for-

mal read request). The state of the FWFT/STAN pin during

FIFO operation determines the mode in use.

Functional Description

The CY7C436X3V is a monolithic, high-speed, low-power,

CMOS Unidirectional Synchronous (clocked) FIFO memory

which supports clock frequencies up to 67 MHz and has read

access times as fast as 10 ns. Two independent 1K/4K/16K x

36 dual-port SRAM FIFOs on board each chip buffer data in

opposite directions. FIFO data on Port B can be output in

36-bit, 18-bit, or 9-bit formats with a choice of big- or little-en-

dian configurations.

The FIFO has a combined Empty/Output Ready flag (EF/OR)

and a combined Full/Input Ready flag (FF/IR). The EF and FF

functions are selected in the CY Standard Mode. EF indicates

whether the memory is full or not. The IR and OR functions are

selected in the First Word Fall Through Mode. IR indicates

whether or not the FIFO has available memory locations. OR

shows whether the FIFO has data available for reading or not.

It marks the presence of valid data on the outputs.

The CY7C436X3V is a synchronous (clocked) FIFO, meaning

each port employs a synchronous interface. All data transfers

through a port are gated to the LOW-to-HIGH transition of a

port clock by enable signals. The clocks for each port are in-

dependent of one another and can be asynchronous or coin-

cident. The enables for each port are arranged to provide a

simple Unidirectional interface between microprocessors

and/or buses with synchronous control.

The FIFO has a programmable Almost Empty flag (AE) and a

programmable Almost Full flag (AF). AE indicates when a se-

lected number of words written to FIFO memory achieve a

predetermined “almost empty state.” AF indicates when a se-

lected number of words written to the memory achieve a pre-

determined “almost full state.”

Communication between each port may bypass the FIFOs via

two mailbox registers. The mailbox registers’ width matches

the selected Port B bus width. Each mailbox register has a flag

(MBF1 and MBF2) to signal when new mail has been stored.

IR and AF are synchronized to the port clock that writes data

into its array. OR and AE are synchronized to the port clock

that reads data from its array. Programmable offset for AE and

AF are loaded in parallel using Port A or in serial via the SD

input. Three default offset settings are also provided. The AE

threshold can be set at 8, 16, or 64 locations from the empty

boundary and AF threshold can be set at 8, 16, or 64 locations

from the full boundary. All these choices are made using the

FS0 and FS1 inputs during Master Reset.

Two kinds of reset are available on the CY7C436X3V: Master

Reset and Partial Reset. Master Reset initializes the read and

write pointers to the first location of the memory array, config-

ures the FIFO for big- or little-endian byte arrangement and

selects serial flag programming, parallel flag programming, or

one of the three possible default flag offset settings, 8, 16, or

64. The FIFO also has a Master Reset pin, MRS1/MRS2.

Partial Reset also sets the read and write pointers to the first

location of the memory. Unlike Master Reset, any settings ex-

isting prior to Partial Reset (i.e., programming method and par-

tial flag default offsets) are retained. Partial Reset is useful

since it permits flushing of the FIFO memory without changing

any configuration settings. The FIFO has its own independent

Partial Reset pin, PRS.

Two or more devices may be used in parallel to create wider

data paths. If any time, the FIFO is not actively performing a

function, the chip will automatically power down. During the

power down state, supply current consumption (I ) is at a

minimum. Initiating any operation (by activating control inputs)

will immediately take the device out of the Power Down state.

The CY7C436X3V have two modes of operation: In the CY

Standard Mode, the first word written to an empty FIFO is de-

posited into the memory array. A read operation is required to

The CY7C436X3V are characterized for operation from 0°C to

70°C. Input ESD protection is greater than 2001V, and latch-up

is prevented by the use of guard rings.

Selection Guide

CY7C43643/63/83V–15

Maximum Frequency (MHz)

Maximum Access Time (ns)

Minimum Cycle Time (ns)

66.7

Minimum Data or Enable Set-Up (ns)

Minimum Data or Enable Hold (ns)

Maximum Flag Delay (ns)

Active Power Supply

Commercial

Industrial

Current (I

) (mA)

CC1

CY7C43643V

CY7C43663V

4K x 36

CY7C43683V

16K x 36

Density

1K x 36

Package

128 TQFP

1 234 5 6 7...27

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与CY7C43643V-15AC相关器件

型号	品牌	描述	获取价格	数据表
CY7C43643V-20AC	CYPRESS	FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-1	获取价格
CY7C43644	CYPRESS	1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching	获取价格
CY7C43644-10AC	CYPRESS	1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching	获取价格
CY7C43644-15AC	CYPRESS	1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching	获取价格
CY7C43644-7AC	CYPRESS	1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching	获取价格
CY7C43644AV	CYPRESS	3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching	获取价格

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