5秒后页面跳转
捷配首页

Datasheet > 存储 > FIFO> CY7C4261V-15JCR
CY7C4261V-15JCR PDF预览

CY7C4261V-15JCR

更新时间： 2024-02-14 12:00:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
16页 455K
描述
FIFO, 16KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

阅读下载

获取价格

CY7C4261V-15JCR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFJ
包装说明：QCCJ, LDCC32,.5X.6针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71Factory Lead Time：1 week
风险等级：8.52最长访问时间：10 ns
最大时钟频率 (fCLK)：66.7 MHz周期时间：15 ns
JESD-30 代码：R-PQCC-J32JESD-609代码：e3
长度：13.97 mm内存密度：147456 bit
内存集成电路类型：OTHER FIFO内存宽度：9
湿度敏感等级：3功能数量：1
端子数量：32字数：16384 words
字数代码：16000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：16KX9输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：3.556 mm最大待机电流：0.004 A
子类别：FIFOs最大压摆率：0.025 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：11.43 mm
Base Number Matches：1

CY7C4261V-15JCR 数据手册

 浏览型号CY7C4261V-15JCR的Datasheet PDF文件第1页浏览型号CY7C4261V-15JCR的Datasheet PDF文件第3页浏览型号CY7C4261V-15JCR的Datasheet PDF文件第4页浏览型号CY7C4261V-15JCR的Datasheet PDF文件第5页浏览型号CY7C4261V-15JCR的Datasheet PDF文件第6页浏览型号CY7C4261V-15JCR的Datasheet PDF文件第7页 
CY7C4261V/CY7C4271V  
CY7C4281V/CY7C4291V  
Selection Guide  
7C4261/71/81/91V-10  
7C4261/71/81/91V-15  
7C4261/71/81/91V-25  
Unit  
MHz  
ns  
Maximum Frequency  
100  
8
66.7  
10  
15  
4
40  
15  
25  
6
Maximum Access Time  
Minimum Cycle Time  
10  
3.5  
0
ns  
Minimum Data or Enable Set-up  
Minimum Data or Enable Hold  
Maximum Flag Delay  
ns  
0
1
ns  
8
10  
25  
30  
15  
25  
ns  
Active Power Supply  
Commercial  
25  
mA  
Current (ICC1  
)
Industrial  
CY7C4261V  
16K x 9  
CY7C4271V  
32K x 9  
CY7C4281V  
64K x 9  
CY7C4291V  
128K x 9  
Density  
Package  
32-pin PLCC  
32-pin PLCC  
32-pin PLCC  
32-pin PLCC  
Pin Definitions  
Signal Name  
Description  
I/O  
Description  
D0−8  
Data Inputs  
I
O
I
Data Inputs for 9-bit bus.  
Data Outputs for 9-bit bus.  
Q0−8  
Data Outputs  
Write Enable 1  
WEN1  
The only write enable when device is configured to have programmable flags.  
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF  
is HIGH. If the FIFO is configured to have two write enables, data is written on a  
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.  
WEN2/LD  
Dual Mode Pin  
Write Enable 2  
Load  
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this  
pin operates as a control to write or read the programmable flag offsets. WEN1 must be  
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into  
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,  
WEN2/LD is held LOW to write or read the programmable flag offsets.  
REN1, REN2 Read Enable  
Inputs  
I
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to  
allow a read operation.  
WCLK  
Write Clock  
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is  
HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the  
programmable flag-offset register.  
RCLK  
Read Clock  
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and  
the FIFO are not Empty. When WEN2/LD is LOW, RCLK reads data out of the program-  
mable flag-offset register.  
EF  
Empty Flag  
Full Flag  
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.  
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.  
FF  
PAE  
Programmable  
Almost Empty  
When PAE is LOW, the FIFO is almost empty based on the almost empty offset  
value programmed into the FIFO. PAE is synchronized to RCLK.  
PAF  
RS  
Programmable  
Almost Full  
O
I
When PAF is LOW, the FIFO is almost full based on the almost full offset value  
programmed into the FIFO. PAF is synchronized to WCLK.  
Reset  
Resets device to empty condition. A reset is required before an initial read or write  
operation after power-up.  
OE  
Output Enable  
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are  
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.  
Document #: 38-06013 Rev. *B  
Page 2 of 16  
1234567...16

下载PDF

与CY7C4261V-15JCR相关器件

型号 品牌 描述 获取价格 数据表
CY7C4261V-15JI CYPRESS 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs

获取价格
CY7C4261V-15JIR CYPRESS FIFO, 16KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

获取价格
CY7C4261V-15JIT CYPRESS FIFO, 16KX9, 10ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

获取价格
CY7C4261V-15JXC CYPRESS 16K/32K/64K/128K x 9 Low-Voltage Deep Sync⑩ F

获取价格
CY7C4261V-25JC CYPRESS 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs

获取价格
CY7C4261V-25JCR CYPRESS FIFO, 16KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

获取价格

与CY7C4261V-15JCR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证