CY7C4261
CY7C4271
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle.
Functional Description (continued)
The CY7C4261/71 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty + 7 and Full – 7.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
Pin Definitions
Signal Name
D0−8
Description I/O
Description
Data Inputs
I
O
I
Data Inputs for 9-bit bus.
Q0−8
Data Outputs
Write Enable 1
Data Outputs for 9-bit bus.
WEN1
The only write enable when device is configured to have programmable flags. Data
is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be LOW
and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the
FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD
is held LOW to write or read the programmable flag offsets.
REN1, REN2 Read Enable
Inputs
I
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
WCLK
Write Clock
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset
value programmed into the FIFO. PAE is synchronized to RCLK.
PAF
RS
Programmable
Almost Full
O
I
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Selection Guide
7C4261/71-10
7C4261/71-15
7C4261/71-25
7C4261/71-35
Unit
MHz
ns
Maximum Frequency
100
8
66.7
10
15
4
40
15
25
6
28.6
20
35
7
Maximum Access Time
Minimum Cycle Time
10
3
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
ns
0.5
8
1
1
2
ns
10
35
40
15
35
40
20
35
40
ns
Active Power Supply Commercial
35
40
mA
Current (ICC1
)
Industrial/
Military
Document #: 38-06015 Rev. *C
Page 2 of 18
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