Datasheet > 存储 > FIFO> CY7C4245-15AXC

CY7C4245-15AXC

更新时间： 2024-11-28 12:43:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
25页	689K
描述
256/512/1K/4K x 18 Synchronous FIFOs

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CY7C4245-15AXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-64
针数：	64	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
Factory Lead Time：	1 week	风险等级：	5.63
最长访问时间：	10 ns	其他特性：	RETRANSMIT
最大时钟频率 (fCLK)：	66.7 MHz	周期时间：	15 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e4
长度：	14 mm	内存密度：	73728 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	64	字数：	4096 words
字数代码：	4000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4KX18	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP64,.63SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.01 A
子类别：	FIFOs	最大压摆率：	0.045 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

CY7C4245-15AXC 数据手册

CY7C4205/CY7C4215

CY7C4225/CY7C4245

256/512/1K/4K x 18 Synchronous FIFOs

Features

Functional Description

■ High speed, low power, first-in first-out (FIFO) memories

■ 256 x 18 (CY7C4205)

The CY7C42X5 are high speed, low power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All are

18 bits wide and are pin/functionally compatible to IDT722X5.

The CY7C42X5 can be cascaded to increase FIFO depth.

Programmable features include Almost Full/Almost Empty flags.

These FIFOs provide solutions for a wide variety of data

buffering needs, including high speed data acquisition, multipro-

cessor interfaces, and communications buffering.

■ 512 x 18 (CY7C4215)

■ 1K x 18 (CY7C4225)

■ 4K x 18 (CY7C4245)

■ High speed 100 MHz operation (10 ns read/write cycle time)

■ Low power (I_CC= 45 mA)

These FIFOs have 18-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and a write enable

pin (WEN). When WEN is asserted, data is written into the FIFO

on the rising edge of the WCLK signal. While WEN is held active,

data is continually written into the FIFO on each cycle. The

output port is controlled in a similar manner by a free-running

read clock (RCLK) and a read enable pin (REN). In addition, the

CY7C42X5 have an output enable pin (OE). The read and write

clocks may be tied together for single-clock operation or the two

clocks may be run independently for asynchronous read/write

applications. Clock frequencies up to 100 MHz are achievable.

■ Fully asynchronous and simultaneous read and write operation

■ Empty, full, half full, and programmable almost empty/almost

Full status flags

■ Transistor-transistor logic (TTL) compatible

■ Retransmit function

■ Output enable (OE) pin

■ Independent read and write enable pins

■ Center power and ground for reduced noise

■ Supports free running 50% duty cycle clock inputs

■ Width expansion capability

Retransmit and synchronous almost full/almost empty flag

features are available on these devices.

Depth expansion is possible using the cascade input (WXI, RXI),

cascade output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of

the next device, and the WXO and RXO pins of the last device

should be connected to the WXI and RXI pins of the first device.

The FL pin of the first device is tied to VSS and the FL pin of all

the remaining devices should be tied to VCC.

■ Depth expansion capability

■ Available in 64 pin 14 x 14 thin quad flat package (TQFP) and

64 pin 10 x 10 TQFP

The CY7C42X5 provides five status pins. These pins are

decoded to determine one of five states: Empty, Almost Empty,

Half Full, Almost Full, and Full (see Table 2). The Half Full flag

shares the WXO pin. This flag is valid in the standalone and

width-expansion configurations. In the depth expansion, this pin

provides the expansion out (WXO) information that is used to

signal the next FIFO when it will be activated.

The Empty and Full flags are synchronous, i.e., they change

state relative to either the read clock (RCLK) or the write clock

(WCLK). When entering or exiting the Empty states, the flag is

updated exclusively by the RCLK. The flag denoting Full states

is updated exclusively by WCLK. The synchronous flag archi-

tecture guarantees that the flags will remain valid from one clock

cycle to the next. As mentioned previously, the Almost

Empty/Almost Full flags become synchronous if the

VCC/SMODE is tied to VSS. All configurations are fabricated

using an advanced 0.65m N-Well CMOS technology. Input ESD

protection is greater than 2001V, and latch-up is prevented by

the use of guard rings.

Cypress Semiconductor Corporation

Document Number: 001-45652 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 25, 2011

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CY7C4245-15AXC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C4245-15AC	CYPRESS	完全替代	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
CY7C4245-15ASXC	CYPRESS	类似代替	256/512/1K/4K x 18 Synchronous FIFOs

与CY7C4245-15AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C4245-15JC	CYPRESS	获取价格	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
CY7C4245-15JCR	CYPRESS	获取价格	FIFO, 4KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4245-15JCT	CYPRESS	获取价格	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4245-15JI	CYPRESS	获取价格	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
CY7C4245-15JXC	ROCHESTER	获取价格	4K X 18 OTHER FIFO, 10 ns, PQCC68, LEAD FREE, PLASTIC, LCC-68
CY7C4245-25AC	CYPRESS	获取价格	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
CY7C4245-25ACT	CYPRESS	获取价格	暂无描述
CY7C4245-25AI	CYPRESS	获取价格	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
CY7C4245-25ASC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4245-25ASI	CYPRESS	获取价格	64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

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