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CY7C4241V-35JC PDF预览

CY7C4241V-35JC

更新时间： 2024-02-06 00:46:41
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
16页 337K
描述
FIFO, 4KX9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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CY7C4241V-35JC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFJ包装说明：PLASTIC, LCC-32
针数：32Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.76Is Samacsys：N
最长访问时间：20 ns最大时钟频率 (fCLK)：28.6 MHz
周期时间：35 nsJESD-30 代码：R-PQCC-J32
JESD-609代码：e0长度：13.97 mm
内存密度：36864 bit内存集成电路类型：OTHER FIFO
内存宽度：9功能数量：1
端子数量：32字数：4096 words
字数代码：4000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4KX9输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：3.55 mm最大待机电流：0.006 A
子类别：FIFOs最大压摆率：0.02 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：11.43 mm
Base Number Matches：1

CY7C4241V-35JC 数据手册

 浏览型号CY7C4241V-35JC的Datasheet PDF文件第2页浏览型号CY7C4241V-35JC的Datasheet PDF文件第3页浏览型号CY7C4241V-35JC的Datasheet PDF文件第4页浏览型号CY7C4241V-35JC的Datasheet PDF文件第5页浏览型号CY7C4241V-35JC的Datasheet PDF文件第6页浏览型号CY7C4241V-35JC的Datasheet PDF文件第7页 
1CY 7 C42 31 V/4 24 1V  
/4 25 1V  
fax id: 5418  
CY7C4421V/4201V/4211V/4221V  
PRELIMINARY  
CY7C4231V/4241V/4251V  
Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs  
• 32-pin PLCC  
Features  
Functional Description  
• High-speed, low-power, first-in, first-out (FIFO)  
memories  
The CY7C42X1V are high-speed, low-power, first-in first-out  
(FIFO) memories with clocked read and write interfaces. All  
are 9 bits wide. Programmable features include Almost  
Full/Almost Empty flags. These FIFOs provide solutions for a  
wide variety of data buffering needs, including high-speed  
data acquisition, multiprocessor interfaces, and communica-  
tions buffering.  
• 64 x 9 (CY7C4421V)  
• 256 x 9 (CY7C4201V)  
• 512 x 9 (CY7C4211V)  
• 1K x 9 (CY7C4221V)  
• 2K x 9 (CY7C4231V)  
• 4K x 9 (CY7C4241V)  
• 8K x 9 (CY7C4251V)  
These FIFOs have 9-bit input and output ports that are con-  
trolled by separate clock and enable signals. The input port is  
controlled by a free-running clock (WCLK) and two write-en-  
able pins (WEN1, WEN2/LD).  
• High-speed 66-MHz operation (15 ns read/write cycle  
time)  
• Low power (I = 20 mA)  
CC  
When WEN1 is LOW and WEN2/LD is HIGH, data is written  
into the FIFO on the rising edge of the WCLK signal. While  
WEN1, WEN2/LD is held active, data is continually written into  
the FIFO on each WCLK cycle. The output port is controlled  
in a similar manner by a free-running read clock (RCLK) and  
two read-enable pins (REN1, REN2). In addition, the  
CY7C42X1V has an output enable pin (OE). The read (RCLK)  
and write (WCLK) clocks may be tied together for single-clock  
operation or the two clocks may be run independently for  
asynchronous read/write applications. Clock frequencies up  
to 66 MHz are achievable.  
• 3.3V operation for low power consumption and easy  
integration into low voltage systems  
• 5V tolerant inputs V  
= 5V  
IH max  
• Fully asynchronous and simultaneous read and write  
operation  
• Empty, Full, and Programmable Almost Empty and  
Almost Full status flags  
• TTL compatible  
• Output Enable (OE) pin  
• Independent read and write enable pins  
• Center power and ground pins for reduced noise  
• Width Expansion Capability  
Depth expansion is possible using one enable input for sys-  
tem control, while the other enable is controlled by expansion  
logic to direct the flow of data  
• Space saving 32-pin 7mm x 7mm TQFP  
.
Pin Configuration  
Logic Block Diagram  
D
0− 8  
PLCC  
Top View  
INPUT  
REGISTER  
4
3
2
1 323130  
29  
28  
D
D
PAF  
PAE  
GND  
REN1  
RCLK  
REN2  
OE  
RS  
WEN1  
1
5
6
7
8
9
0
27 WCLK  
26  
25  
24  
23  
22  
21  
WCLKWEN1 WEN2/LD  
WEN2/LD  
V
CC  
FLAG  
PROGRAM  
REGISTER  
Q
Q
Q
Q
10  
11  
12  
13  
8
7
6
5
WRITE  
CONTROL  
14151617181920  
EF  
42X1V–2  
PAE  
PAF  
FF  
FLAG  
LOGIC  
Dual Port  
RAM Array  
64 x 9  
TQFP  
Top View  
WRITE  
POINTER  
READ  
POINTER  
8k x 9  
32 31 30 2928 27 26 25  
1
2
3
4
5
6
7
8
24  
23  
WEN1  
D
D
1
0
RESET  
LOGIC  
RS  
WCLK  
WEN2/LD  
22  
21  
20  
19  
PAF  
PAE  
GND  
REN1  
V
CC  
THREE-STATE  
OUTPUTREGISTER  
Q
Q
8
7
READ  
CONTROL  
Q
Q
6
5
RCLK  
REN2  
18  
17  
OE  
9 10 11 12 13 14 15 16  
Q
0 − 8  
RCLK REN1 REN2  
42X1V–3  
42X1V–1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
June 1997 – Revised August 18, 1997  
1234567...16

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与CY7C4241V-35JC相关器件

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CY7C4241V-35JCR CYPRESS

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 		FIFO, 4KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4241V-35JCT CYPRESS

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 		FIFO, 4KX9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C424-20DC ETC

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 		x9 Asynchronous FIFO
CY7C424-25DC CYPRESS

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 		FIFO, 1KX9, 25ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C424-25DI ETC

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 		x9 Asynchronous FIFO
CY7C424-30DC CYPRESS

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 		暂无描述
CY7C424-30DI CYPRESS

获取价格

 		FIFO, 1KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C424-30PI CYPRESS

获取价格

 		FIFO, 1KX9, 30ns, Asynchronous, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
CY7C424-40DC CYPRESS

获取价格

 		FIFO, 1KX9, 40ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28
CY7C424-40DI CYPRESS

获取价格

 		FIFO, 1KX9, 40ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERDIP-28

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