Datasheet > 存储 > FIFO> CY7C4225-15AXC

CY7C4225-15AXC

更新时间： 2024-01-22 15:57:45

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
25页	689K
描述
256/512/1K/4K x 18 Synchronous FIFOs

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C4225-15AXC 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	68
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.49
最长访问时间：	10 ns	其他特性：	RETRANSMIT
周期时间：	15 ns	JESD-30 代码：	S-PQCC-J68
长度：	24.2316 mm	内存密度：	18432 bit
内存宽度：	18	功能数量：	1
端子数量：	68	字数：	1024 words
字数代码：	1000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	24.2316 mm
Base Number Matches：	1

CY7C4225-15AXC 数据手册

CY7C4205/CY7C4215

CY7C4225/CY7C4245

Pin Definitions (continued)

Signal Name

Description

Function

RXO

Read expansion

output

Cascaded – Connected to RXI of next device.

Reset

Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

Output enable

When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.

If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

V_CC/SMODE Synchronous

almost empty/

Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to V_CC.

Synchronous Almost Empty/Almost Full flags – tied to V_SS. (Almost Empty synchro-

nized to RCLK, Almost Full synchronized to WCLK.)

almost full flags

Architecture

Programming

The CY7C42X5 consists of an array of 256 to 1 K words & 4 K

words of 18 bits each (implemented by a dual-port array of

SRAM cells), a read pointer, a write pointer, control signals

(RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF,

FF). The CY7C42X5 also includes the control signals WXI, RXI,

WXO, RXO for depth expansion.

The CY7C42X5 devices contain two 12-bit offset registers. Data

present on D_0–11during a program write will determine the

distance from Empty (Full) that the Almost Empty (Almost Full)

flags become active. If the user elects not to program the FIFO’s

flags, the default offset values are used (see Table 2). When the

Load LD pin is set LOW and WEN is set LOW, data on the inputs

D_0–11is written into the Empty offset register on the first

LOW-to-HIGH transition of the write clock (WCLK). When the LD

pin and WEN are held LOW then data is written into the Full offset

Clock (WCLK). The third transition of the Write Clock (WCLK)

again writes to the Empty offset register (see Table 1). Writing all

offset registers does not have to occur at one time. One or two

offset registers can be written and then, by bringing the LD pin

HIGH, the FIFO is returned to normal read/write operation. When

the LD pin is set LOW, and WEN is LOW, the next offset register

in sequence is written.

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS) cycle.

This causes the FIFO to enter the Empty condition signified by

EF being LOW. All data outputs go LOW after the falling edge of

RS only if OE is asserted. In order for the FIFO to reset to its

default state, a falling edge must occur on RS and the user must

not read or write while RS is LOW.

FIFO Operation

The contents of the offset registers can be read on the output

lines when the LD pin is set LOW and REN is set LOW; then,

data can be read on the LOW-to-HIGH transition of the Read

Clock (RCLK).

When the WEN signal is active (LOW), data present on the D_0-17

pins is written into the FIFO on each rising edge of the WCLK

signal. Similarly, when the REN signal is active LOW, data in the

FIFO memory will be presented on the Q_017outputs. New data

will be presented on each rising edge of RCLK while REN is

active LOW and OE is LOW. REN must set up t_ENSbefore RCLK

for it to be a valid read function. WEN must occur t_ENSbefore

WCLK for it to be a valid write function.

Table 1. Write Offset Register

LD WEN WCLK^[1]

Selection

Writing to offset registers:

Empty Offset

An Output Enable (OE) pin is provided to three-state the Q_0–17

outputs when OE is deasserted. When OE is enabled (LOW),

data in the output register will be available to the Q_017outputs

after t_OE. If devices are cascaded, the OE function will only

output data on the FIFO that is read enabled.

Full Offset

No operation

Write into FIFO

No operation

The FIFO contains overflow circuitry to disallow additional writes

when the FIFO is full, and underflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

maintains the data of the last valid read on its Q_017outputs even

after additional reads occur.

Note

1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Document Number: 001-45652 Rev. *B

Page 6 of 25

[+] Feedback

1...3 4 567 8 9...25

下载PDF

与CY7C4225-15AXC相关器件

型号	品牌	描述	获取价格	数据表
CY7C4225-15AXCT	CYPRESS	FIFO, 1KX18, 10ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, LEAD FREE, PLASTIC, TQFP-64	获取价格
CY7C4225-15JC	CYPRESS	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs	获取价格
CY7C4225-15JCT	CYPRESS	FIFO, 1KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68	获取价格
CY7C4225-15JI	CYPRESS	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs	获取价格
CY7C4225-15JIR	CYPRESS	FIFO, 1KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68	获取价格
CY7C4225-15JIT	CYPRESS	FIFO, 1KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68	获取价格

与CY7C4225-15AXC相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

13
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C4225-15AXC

CY7C4225-15AXC 技术参数

CY7C4225-15AXC 数据手册

与CY7C4225-15AXC相关器件

与CY7C4225-15AXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C4225-15AXC

CY7C4225-15AXC 技术参数

CY7C4225-15AXC 数据手册

与CY7C4225-15AXC相关器件

与CY7C4225-15AXC相关文章

您还可以找

您在本页遇到什么问题？