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CY7C408A-409A PDF预览

CY7C408A-409A

更新时间: 2022-02-02 04:57:44
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
16页 347K
描述
64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO

CY7C408A-409A 数据手册

 浏览型号CY7C408A-409A的Datasheet PDF文件第1页浏览型号CY7C408A-409A的Datasheet PDF文件第2页浏览型号CY7C408A-409A的Datasheet PDF文件第4页浏览型号CY7C408A-409A的Datasheet PDF文件第5页浏览型号CY7C408A-409A的Datasheet PDF文件第6页浏览型号CY7C408A-409A的Datasheet PDF文件第7页 
CY7C408A  
CY7C409A  
[3, 6]  
Switching Characteristics Over the Operating Range  
7C408A-15  
7C409A-15  
7C408A-25  
7C409A-25  
7C408A-35  
7C409A-35  
Test  
Parameter  
Description  
Operating Frequency  
SI HIGH Time  
Conditions Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 7  
15  
25  
35  
O
Note 7  
Note 7  
Note 8  
Note 8  
23  
25  
0
11  
24  
0
9
PHSI  
PLSI  
SSI  
SI LOW Time  
17  
0
Data Set-Up to SI  
Data Hold from SI  
30  
20  
12  
HSI  
Delay, SI HIGH to IR LOW  
Delay, SI LOW to IR HIGH  
SO HIGH Time  
35  
40  
21  
23  
15  
16  
DLIR  
DHIR  
PHSO  
PLSO  
DLOR  
DHOR  
SOR  
HSO  
BT  
Note 7  
Note 7  
23  
25  
11  
24  
9
SO LOW Time  
17  
Delay, SO HIGH to OR LOW  
Delay, SO LOW to OR HIGH  
Data Set-Up to OR HIGH  
Data Hold from SO LOW  
Fall-through, Bubble-back Time  
Data Set-Up to IR  
35  
40  
21  
23  
15  
16  
0
0
0
0
0
0
10  
5
65  
10  
5
60  
10  
5
50  
Note 9  
Note 9  
SIR  
Data Hold from IR  
30  
6
20  
6
20  
6
HIR  
Input Ready Pulse HIGH  
Output Ready Pulse HIGH  
OE LOW to LOW Z (7C408A)  
OE HIGH to HIGH Z (7C408A)  
SI LOW to HF HIGH  
Note 10  
Note 11  
Note 12  
Note 7  
PIR  
6
6
6
POR  
DLZOE  
DHZOE  
DHHF  
DLHF  
DLAFE  
DHAFE  
PMR  
DSI  
35  
35  
65  
65  
65  
65  
30  
30  
55  
55  
55  
55  
25  
25  
45  
45  
45  
45  
SO LOW to HF LOW  
SO or SI LOW to AFE LOW  
SO or SI LOW to AFE HIGH  
MR Pulse Width  
55  
25  
45  
10  
35  
10  
MR HIGH to SI HIGH  
MR LOW to OR LOW  
MR LOW to IR HIGH  
MR LOW to Output LOW  
MR LOW to AFE HIGH  
MR LOW to HF LOW  
SO LOW to Next Data Out Valid  
55  
55  
55  
55  
55  
28  
45  
45  
45  
45  
45  
20  
35  
35  
35  
35  
35  
16  
DOR  
DIR  
Note 13  
LZMR  
AFE  
HF  
OD  
Notes:  
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load  
capacitance, as in parts (a) and (b) of AC Test Loads and Waveforms.  
7. 1/fO > (tPHSI + tPLSI), 1/fO > (tPHSO + tPLSO).  
8. tSSI and tHSI apply when memory is not full.  
9. tSIR and tHIR apply when memory is full, SI is high and minimum bubble-through (tBT) conditions exist.  
10. At any given operating condition tPIR > (tPHSO required).  
11. At any given operating condition tPOR > (tPHSI required).  
12. tDHZOE and tDLZOE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. tDHZOE transition is measured ±500 mV from steady-state  
voltage. tDLZOE transition is measured ±100 mV from steady-state voltage. These parameters are guaranteed and not 100% tested.  
13. All data outputs will be at LOW level after reset goes HIGH until data is entered into the FIFO.  
3

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64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO