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CY7C342B-25RMB PDF预览

CY7C342B-25RMB

更新时间： 2024-11-21 13:07:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 351K
描述
UV PLD, 51ns, 128-Cell, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68

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CY7C342B-25RMB 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：PGA包装说明：WINDOWED, CERAMIC, PGA-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.85Is Samacsys：N
其他特性：LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK最大时钟频率：33.3 MHz
系统内可编程：NOJESD-30 代码：S-CPGA-P68
JESD-609代码：e0JTAG BST：NO
长度：27.9527 mm专用输入次数：7
I/O 线路数量：52宏单元数：128
端子数量：68最高工作温度：125 °C
最低工作温度：-55 °C组织：7 DEDICATED INPUTS, 52 I/O
输出函数：MACROCELL封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：WPGA封装等效代码：PGA68,11X11
封装形状：SQUARE封装形式：GRID ARRAY, WINDOW
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
可编程逻辑类型：UV PLD传播延迟：51 ns
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：5.08 mm子类别：Programmable Logic Devices
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：PIN/PEG
端子节距：2.54 mm端子位置：PERPENDICULAR
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：27.9527 mm
Base Number Matches：1

CY7C342B-25RMB 数据手册

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USE ULTRA37000TM FOR  
ALL NEW DESIGNS  
CY7C342B  
128-Macrocell MAX® EPLD  
100% user-configurable, allowing the device to accommodate  
a variety of independent logic functions.  
Features  
• 128 macrocells in eight logic array blocks (LABs)  
• Eight dedicated inputs, 52 bidirectional I/O pins  
• Programmable interconnect array  
The 128 macrocells in the CY7C342B are divided into eight  
LABs, 16 per LAB. There are 256 expander product terms, 32  
per LAB, to be used and shared by the macrocells within each  
LAB.  
• Advanced 0.65-micron CMOS technology to increase  
performance  
Each LAB is interconnected with a programmable interconnect  
array, allowing all signals to be routed throughout the chip.  
• Available in 68-pin HLCC, PLCC, and PGA packages  
The speed and density of the CY7C342B allows it to be used in a  
wide range of applications, from replacement of large amounts of  
7400-series TTL logic, to complex controllers and multifunction  
chips. With greater than 25 times the functionality of 20-pin PLDs,  
the CY7C342B allows the replacement of over 50 TTL devices.  
By replacing large amounts of logic, the CY7C342B reduces board  
space, part count, and increases system reliability.  
Functional Description  
The CY7C342B is an Erasable Programmable Logic Device  
(EPLD) in which CMOS EPROM cells are used to configure  
logic functions within the device. The MAX® architecture is  
LogicBlock Diagram  
1 (B6) INPUT/CLK  
INPUT  
INPUT  
INPUT  
INPUT  
(A7) 68  
(A8) 66  
(L6) 36  
(K6) 35  
2 (A6)  
32 (L4)  
34 (L5)  
INPUT  
INPUT  
INPUT  
SYSTEM CLOCK  
LABA  
LABH  
(B8) 65  
(A9) 64  
(B9) 63  
(A10) 62  
(B10) 61  
(B11) 60  
(C11) 59  
(C10) 58  
MACROCELL 1  
MACROCELL 2  
MACROCELL 3  
MACROCELL 4  
MACROCELL 5  
MACROCELL 6  
MACROCELL 7  
MACROCELL 8  
MACROCELL 120  
MACROCELL 119  
MACROCELL 118  
MACROCELL 117  
MACROCELL 116  
MACROCELL 115  
MACROCELL 114  
MACROCELL 113  
4 (A5)  
5 (B4)  
6 (A4)  
7 (B3)  
8 (A3)  
9 (A2)  
10 (B2)  
11 (B1)  
MACROCELL 9–16  
MACROCELL 121–128  
LAB B  
LABG  
12 (C2)  
13 (C1)  
14 (D2)  
15 (D1)  
17 (E1)  
(D11) 57  
(D10) 56  
(E11) 55  
(F11) 53  
(F10) 52  
MACROCELL 101  
MACROCELL 100  
MACROCELL 99  
MACROCELL 98  
MACROCELL 97  
MACROCELL 17  
MACROCELL 18  
MACROCELL 19  
MACROCELL 20  
MACROCELL 21  
MACROCELL 22–32  
MACROCELL 102–112  
P
I
A
LABC  
LAB F  
18 (F2)  
19 (F1)  
21 (G1)  
22 (H2)  
23 (H1)  
(G11) 51  
(H11) 49  
(H10) 48  
(J11) 47  
(J10) 46  
MACROCELL 33  
MACROCELL 34  
MACROCELL 35  
MACROCELL 36  
MACROCELL 37  
MACROCELL 85  
MACROCELL 84  
MACROCELL 83  
MACROCELL 82  
MACROCELL 81  
MACROCELL 38–48  
MACROCELL 86–96  
LAB D  
LABE  
MACROCELL 49  
MACROCELL 50  
MACROCELL 51  
MACROCELL 52  
MACROCELL 53  
MACROCELL 54  
MACROCELL 55  
MACROCELL 56  
(K11) 45  
(K10) 44  
(L10) 43  
(L9) 42  
(K9) 41  
(L8) 40  
(K8) 39  
(L7) 38  
MACROCELL 72  
MACROCELL 71  
MACROCELL 70  
MACROCELL 69  
MACROCELL 68  
MACROCELL 67  
MACROCELL 66  
MACROCELL 65  
24 (J2)  
25 (J1)  
26 (K1)  
27 (K2)  
28 (L2)  
29 (K3)  
30 (L3)  
31 (K4)  
MACROCELL 73–80  
MACROCELL 57–64  
() –PERTAIN TO 68-PIN PGA PACKAGE  
3, 20, 37, 54 (B5, G2, K7, E10)  
16, 33, 50, 67 (E2, K5, G10, B7)  
V
CC  
GND  
Cypress Semiconductor Corporation  
Document #: 38-03014 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised April 22, 2004  
1234567...14

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