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CY7C2642KV18-333BZXC PDF预览

CY7C2642KV18-333BZXC

更新时间： 2024-02-24 18:43:58
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
30页 885K
描述
144-Mbit QDR® II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT

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CY7C2642KV18-333BZXC 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LBGA, BGA165,11X15,40Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.77
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：333 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：150994944 bit
内存集成电路类型：QDR SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：8388608 words
字数代码：8000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：8MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最小待机电流：1.7 V子类别：SRAMs
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：15 mm

CY7C2642KV18-333BZXC 数据手册

 浏览型号CY7C2642KV18-333BZXC的Datasheet PDF文件第2页浏览型号CY7C2642KV18-333BZXC的Datasheet PDF文件第3页浏览型号CY7C2642KV18-333BZXC的Datasheet PDF文件第4页浏览型号CY7C2642KV18-333BZXC的Datasheet PDF文件第5页浏览型号CY7C2642KV18-333BZXC的Datasheet PDF文件第6页浏览型号CY7C2642KV18-333BZXC的Datasheet PDF文件第7页 
CY7C2642KV18/CY7C2644KV18  
144-Mbit QDR® II+ SRAM Two-Word  
Burst Architecture (2.0 Cycle Read Latency) with ODT  
144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT  
■ Phase Locked Loop (PLL) for accurate data placement  
Features  
Configurations  
■ Separate independent read and write data ports  
❐ Supports concurrent transactions  
With Read Cycle Latency of 2.0 cycles:  
CY7C2642KV18 – 8 M × 18  
■ 333-MHz clock for high bandwidth  
■ Two-word burst for reducing address bus frequency  
CY7C2644KV18 – 4 M × 36  
■ Double data rate (DDR) interfaces on both read and write ports  
(data transferred at 666 MHz) at 333 MHz  
Functional Description  
■ Available in 2.0-clock cycle latency  
The CY7C2642KV18, and CY7C2644KV18 are 1.8-V  
synchronous pipelined SRAMs, equipped with QDR® II+  
architecture. Similar to QDR II architecture, QDR II+ architecture  
consists of two separate ports: the read port and the write port to  
access the memory array. The read port has dedicated data  
outputs to support read operations and the write port has  
dedicated data inputs to support write operations. QDR II+  
architecture has separate data inputs and data outputs to  
completely eliminate the need to “turn around” the data bus that  
exists with common I/O devices. Access to each port is through  
a common address bus. Addresses for read and write addresses  
are latched on alternate rising edges of the input (K) clock.  
Accesses to the QDR II+ read and write ports are completely  
independent of one another. To maximize data throughput, both  
read and write ports are equipped with DDR interfaces. Each  
address location is associated with two 18-bit words  
(CY7C2642KV18), or 36-bit words (CY7C2644KV18) that burst  
sequentially into or out of the device. Because data can be  
transferred into and out of the device on every rising edge of both  
input clocks (K and K), memory bandwidth is maximized while  
simplifying system design by eliminating bus “turn arounds”.  
■ Two input clocks (K and K) for precise DDR timing  
❐ SRAM uses rising edges only  
■ Echo clocks (CQ and CQ) simplify data capture in high-speed  
systems  
■ Data valid pin (QVLD) to indicate valid data on the output  
■ On-die termination (ODT) feature  
❐ Supported for D[x:0], BWS[x:0], and K/K inputs  
■ Single multiplexed address input bus latches address inputs  
for both read and write ports  
■ Separate port selects for depth expansion  
■ Synchronous internally self-timed writes  
■ Quad data rate (QDR®) II+ operates with 2.0-cycle read latency  
when DOFF is asserted high  
■ Operates similar to QDR I device with one cycle read latency  
when DOFF is asserted low  
■ Available in × 18, and × 36 configurations  
These devices have an ODT feature supported for D[x:0]  
,
■ Full data coherency, providing most current data  
BWS[x:0], and K/K inputs, which helps eliminate external  
termination resistors, reduce cost, reduce board area, and  
simplify board routing.  
[1]  
■ Core VDD = 1.8 V± 0.1 V; I/O VDDQ = 1.4 V to VDD  
❐ Supports both 1.5 V and 1.8 V I/O supply  
Depth expansion is accomplished with port selects, which  
enables each port to operate independently.  
■ High-speed transceiver logic (HSTL) inputs and variable drive  
HSTL output buffers  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the K or K input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
■ Available in 165-ball fine pitch ball grid array (FBGA) package  
(15 × 17 × 1.4 mm)  
■ Offered in both Pb-free and non Pb-free packages  
■ JTAG 1149.1 compatible test access port  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum operating frequency  
333 MHz  
333  
300 MHz Unit  
300 MHz  
Maximum operating current  
× 18  
× 36  
970  
Not Offered mA  
1080  
1160  
Note  
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V  
= 1.4 V to V  
.
DD  
DDQ  
Cypress Semiconductor Corporation  
Document Number: 001-44138 Rev. *P  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 31, 2015  
1234567...30

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