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CY7C199B-20DMB PDF预览

CY7C199B-20DMB

更新时间： 2024-12-01 05:09:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
15页 258K
描述
32K x 8 Static RAM

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中文翻译

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CY7C199B-20DMB 数据手册

 浏览型号CY7C199B-20DMB的Datasheet PDF文件第2页浏览型号CY7C199B-20DMB的Datasheet PDF文件第3页浏览型号CY7C199B-20DMB的Datasheet PDF文件第4页浏览型号CY7C199B-20DMB的Datasheet PDF文件第5页浏览型号CY7C199B-20DMB的Datasheet PDF文件第6页浏览型号CY7C199B-20DMB的Datasheet PDF文件第7页 
PRELIMINARY  
CY7C199B  
32K x 8 Static RAM  
is provided by an active LOW Chip Enable (CE) and active  
LOW Output Enable (OE) and three-state drivers. This device  
has an automatic power-down feature, reducing the power  
consumption by 81% when deselected. The CY7C199B is in  
the standard 300-mil-wide DIP, SOJ, and LCC packages.  
Features  
• High speed  
— 10 ns  
• Fast t  
DOE  
An active LOW Write Enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE and WE inputs  
• CMOS for optimum speed/power  
• Low active power  
are both LOW, data on the eight data input/output pins (I/O  
0
— 495 mW (max, 10 ns “L” version)  
• Low standby power  
through I/O ) is written into the memory location addressed by  
7
the address present on the address pins (A through A ).  
0
14  
Reading the device is accomplished by selecting the device  
and enabling the outputs, CE and OE active LOW, while WE  
remains inactive or HIGH. Under these conditions, the con-  
tents of the location addressed by the information on address  
pins are present on the eight data input/output pins.  
— 0.275 mW (max, “L” version)  
• 2V data retention (“L” version only)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. A die coat is used to improve alpha immunity.  
Functional Description  
The CY7C199B is a high-performance CMOS static RAM or-  
ganized as 32,768 words by 8 bits. Easy memory expansion  
Logic Block Diagram  
Pin Configurations  
DIP / SOJ / SOIC  
Top View  
LCC  
Top View  
A
A
V
CC  
28  
27  
26  
5
1
2
3
4
5
6
WE  
6
3
2 1 2827  
26  
A
A
A
4
7
4
A
4
A
8
8
A
3
25  
24  
5
6
7
8
25  
24  
23  
22  
21  
20  
19  
18  
A
A
9
3
A
9
A
2
A
A
10  
11  
12  
2
A
10  
A
11  
23  
22  
A
1
A
A
A
A
A
1
OE  
7
OE  
9
13  
14  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A
A
A
I/O  
I/O  
I/O  
A
21  
20  
19  
18  
17  
16  
15  
12  
13  
14  
A
0
0
1
2
3
4
5
6
0
8
9
10  
11  
12  
13  
10  
11  
12  
CE  
I/O  
I/O  
INPUT BUFFER  
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
0
7
6
7
1
A
0
0
1
2
6
5
4
1314151617  
A
1
C199–3  
A
2
I/O  
I/O  
A
3
GND  
14  
3
A
4
C199B–2  
1024 x 32 x 8  
ARRAY  
A
5
22  
OE  
A
A
A
0
21  
6
23  
24  
1
A
20  
CE  
I/O  
I/O  
6
I/O  
I/O  
I/O  
GND  
7
A
A
A
A
2
3
4
19  
18  
17  
16  
8
A
7
25  
26  
27  
28  
1
9
5
TSOP I  
Top View  
(not to scale)  
WE  
4
3
CE  
V
CC  
A
A
15  
14  
13  
POWER  
DOWN  
WE  
COLUMN  
DECODER  
5
6
7
2
3
I/O  
2
A
A
A
I/O  
7
12  
11  
I/O  
I/O  
A
1
0
OE  
4
5
8
9
C199B–1  
10  
9
14  
A
6
7
10  
A
A
13  
12  
A
11  
8
C199–4  
Selection Guide  
199B-8  
199B-10  
10  
199B-12  
12  
199B-15  
15  
199B-20  
20  
199B-25  
25  
199B-35  
35  
199B-45  
45  
Maximum Access Time (ns)  
Maximum Operating  
8
120  
110  
160  
90  
155  
90  
150  
90  
150  
80  
140  
70  
140  
Current (mA)  
L
90  
Maximum CMOS  
0.5  
0.5  
10  
10  
10  
10  
10  
10  
Standby Current (mA)  
L
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
Shaded area contains advance information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
June 13, 2000  
1234567...15

中文翻译

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