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CY7C182-25PC PDF预览

CY7C182-25PC

更新时间: 2024-09-29 22:39:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
6页 145K
描述
8Kx9 Static RAM

CY7C182-25PC 数据手册

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CY7C182  
8Kx9 Static RAM  
The CY7C182, which is oriented toward cache memory appli-  
cations, features fully static operation requiring no external  
clocks or timing strobes. The automatic power-down feature  
reduces the power consumption by more than 70% when the  
circuit is deselected. Easy memory expansion is provided by  
Features  
• High speed  
— t = 25 ns  
AA  
• x9 organization is ideal for cache memory applications  
• CMOS for optimum speed/power  
• Low active power  
an active-LOW Chip Enable (CE ), an active HIGH Chip En-  
1
able (CE ), an active-LOW Output Enable (OE), and three-  
2
state drivers.  
— 770 mW  
An active-LOW Write Enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE and WE in-  
puts are both LOW, data on the nine data input/output pins  
• Low standby power  
1
— 195 mW  
(I/O through I/O ) is written into the memory location ad-  
0
8
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• Easy memory expansion with CE , CE , OE options  
dressed by the address present on the address pins (A  
0
through A ). Reading the device is accomplished by selecting  
12  
the device and enabling the outputs, (CE and OE active LOW  
1
1
2
and CE active HIGH), while (WE) remains inactive or HIGH.  
2
Functional Description  
Under these conditions, the contents of the location addressed  
by the information on address pins is present on the nine data  
input/output pins.  
The CY7C182 is a high-speed CMOS static RAM organized  
as 8,192 by 9 bits and it is manufactured using Cypress’s high-  
performance CMOS technology. Access times as fast as 25 ns  
are available with maximum power consumption of only 770  
mW.  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
A die coat is used to insure alpha immunity.  
Logic Block Diagram  
PinConfiguration  
DIP/SOJ  
Top View  
A
A
A
A
A
A
V
CC  
4
5
6
7
8
9
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
WE  
CE  
2
I/O  
0
3
2
INPUT BUFFER  
A
3
4
I/O  
1
A
2
5
A
1
6
I/O  
2
A
1
A
OE  
10  
7
A
2
A
A
A
0
11  
12  
8
I/O  
3
A
3
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
9
1
8
7
6
5
4
A
256 x 32 x 9  
ARRAY  
4
I/O  
I/O  
I/O  
I/O  
10  
11  
12  
13  
14  
0
1
2
3
A
5
I/O  
4
A
6
A
7
I/O  
5
A
8
GND  
I/O  
6
C182–2  
POWER  
DOWN  
CE  
I/O  
7
1
COLUMN  
DECODER  
CE  
2
WE  
I/O  
8
OE  
C182–1  
Selection Guide  
7C182-25  
7C182-35  
7C182-45  
Maximum Access Time (ns)  
25  
140  
35  
35  
140  
35  
45  
140  
35  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 4, 1999  

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