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CY7C182-35PC PDF预览

CY7C182-35PC

更新时间: 2024-09-30 19:51:51
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
7页 152K
描述
Cache SRAM, 8KX9, 35ns, CMOS, PDIP28, 0.300 INCH, DIP-28

CY7C182-35PC 技术参数

生命周期:Contact Manufacturer包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.32.00.41
风险等级:5.71Is Samacsys:N
最长访问时间:35 ns其他特性:AUTOMATIC POWER-DOWN
JESD-30 代码:R-PDIP-T28长度:35.4965 mm
内存密度:73728 bit内存集成电路类型:CACHE SRAM
内存宽度:9功能数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX9封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
座面最大高度:4.826 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

CY7C182-35PC 数据手册

 浏览型号CY7C182-35PC的Datasheet PDF文件第2页浏览型号CY7C182-35PC的Datasheet PDF文件第3页浏览型号CY7C182-35PC的Datasheet PDF文件第4页浏览型号CY7C182-35PC的Datasheet PDF文件第5页浏览型号CY7C182-35PC的Datasheet PDF文件第6页浏览型号CY7C182-35PC的Datasheet PDF文件第7页 
182  
CY7C182  
8Kx9 Static RAM  
The CY7C182, which is oriented toward cache memory appli-  
cations, features fully static operation requiring no external  
clocks or timing strobes. The automatic power-down feature  
reduces the power consumption by more than 70% when the  
circuit is deselected. Easy memory expansion is provided by  
an active-LOW Chip Enable (CE1), an active HIGH Chip En-  
able (CE2), an active-LOW Output Enable (OE), and three-  
state drivers.  
Features  
• High speed  
— tAA = 25 ns  
• x9 organization is ideal for cache memory applications  
• CMOS for optimum speed/power  
• Low active power  
— 770 mW  
An active-LOW Write Enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE1 and WE in-  
puts are both LOW, data on the nine data input/output pins  
(I/O0 through I/O8) is written into the memory location ad-  
dressed by the address present on the address pins (A0  
through A12). Reading the device is accomplished by selecting  
the device and enabling the outputs, (CE1 and OE active LOW  
and CE2 active HIGH), while (WE) remains inactive or HIGH.  
Under these conditions, the contents of the location addressed  
by the information on address pins is present on the nine data  
input/output pins.  
• Low standby power  
— 195 mW  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• Easy memory expansion with CE1, CE2, OE options  
Functional Description  
The CY7C182 is a high-speed CMOS static RAM organized  
as 8,192 by 9 bits and it is manufactured using Cypresss high-  
performance CMOS technology. Access times as fast as 25 ns  
are available with maximum power consumption of only 770  
mW.  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
A die coat is used to insure alpha immunity.  
Logic Block Diagram  
PinConfiguration  
DIP/SOJ  
Top View  
A
A
A
A
A
A
V
CC  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
4
5
6
7
8
9
WE  
CE  
2
I/O  
0
3
2
A
3
INPUT BUFFER  
4
I/O  
1
A
2
5
A
1
6
I/O  
2
A
1
A
A
A
OE  
7
10  
11  
12  
A
2
A
0
8
I/O  
3
A
3
CE  
I/O  
9
1
A
4
256 x 32 x 9  
ARRAY  
I/O  
I/O  
I/O  
I/O  
10  
11  
12  
13  
14  
0
1
2
3
8
7
6
5
4
A
5
I/O  
4
I/O  
I/O  
I/O  
I/O  
A
6
A
7
I/O  
5
A
8
GND  
I/O  
6
C1822  
POWER  
DOWN  
CE  
I/O  
7
1
COLUMN  
DECODER  
CE  
2
WE  
I/O  
8
OE  
C1821  
Selection Guide  
7C182-25  
7C182-35  
7C182-45  
Maximum Access Time (ns)  
25  
140  
35  
35  
140  
35  
45  
140  
35  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05031 Rev. **  
Revised August 24, 2001  

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