Datasheet > CY7C1556KV18

CY7C1556KV18

更新时间： 2024-11-21 00:56:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	691K
描述
72-Mbit QDRÂ®II SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency)

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数据手册

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CY7C1556KV18 数据手册

CY7C1541KV18, CY7C1556KV18

CY7C1543KV18, CY7C1545KV18

72-Mbit QDR^®II+ SRAM 4-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.0 cycles:

CY7C1541KV18 – 8M x 8

■ 450 MHz clock for high bandwidth

CY7C1556KV18 – 8M x 9

CY7C1543KV18 – 4M x 18

CY7C1545KV18 – 2M x 36

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write

ports (data transferred at 900 MHz) at 450 MHz

Functional Description

■ Available in 2.0 clock cycle latency

The CY7C1541KV18, CY7C1556KV18, CY7C1543KV18, and

CY7C1545KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR II+ architecture. Similar to QDR II archi-

tecture, QDR II+ architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus that exists with common IO devices. Each port is

accessed through a common address bus. Addresses for read

and write addresses are latched on alternate rising edges of the

input (K) clock. Accesses to the QDR II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 8-bit

words (CY7C1541KV18), 9-bit words (CY7C1556KV18), 18-bit

words (CY7C1543KV18), or 36-bit words (CY7C1545KV18) that

burst sequentially into or out of the device. Because data is trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II+ operates with 2.0 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

[1]

■ Core V_DD= 1.8V± 0.1V; IO V_DDQ= 1.4V to V_DD

❐ Supports both 1.5V and 1.8V IO supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Phase-Locked Loop (PLL) for accurate data placement

Table 1. Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

450 MHz

400 MHz

400

375 MHz

375

333 MHz

333

Unit

MHz

450

760

780

1100

690

660

600

690

660

600

x18

x36

710

680

620

1000

950

850

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-15700 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 31, 2009

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与CY7C1556KV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1556V18	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-300BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-300BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-300BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-300BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-333BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-333BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-333BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-333BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1556V18-375BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu

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