Datasheet > CY7C1518KV18-250BZI

CY7C1518KV18-250BZI

更新时间： 2024-11-25 11:10:43

品牌	Logo	应用领域
英飞凌 - INFINEON		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
32页	790K
描述
DDR-II CIO

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1518KV18-250BZI 数据手册

浏览型号CY7C1518KV18-250BZI的Datasheet PDF文件第2页

浏览型号CY7C1518KV18-250BZI的Datasheet PDF文件第3页

浏览型号CY7C1518KV18-250BZI的Datasheet PDF文件第4页

浏览型号CY7C1518KV18-250BZI的Datasheet PDF文件第5页

浏览型号CY7C1518KV18-250BZI的Datasheet PDF文件第6页

CY7C1518KV18

CY7C1520KV18

72-Mbit DDR-II SRAM Two-Word

Burst Architecture

72-Mbit DDR-II SRAM Two-Word Burst Architecture

Features

Configurations

■ 72-Mbit density (4M × 18, 2M × 36)

CY7C1518KV18 – 4M × 18

CY7C1520KV18 – 2M × 36

■ 333 MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) interfaces (data transferred at

666 MHz) at 333 MHz

The CY7C1518KV18, and CY7C1520KV18 are 1.8 V

synchronous pipelined SRAM equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced

synchronous peripheral circuitry and a 1-bit burst counter.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of C and C if provided, or on the rising edge of K and K if C/C are

not provided. On CY7C1518KV18 and CY7C1520KV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1518KV18 and two 36-bit words in the case of

CY7C1520KV18 sequentially into or out of the device.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Synchronous internally self-timed writes

■ DDR II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates similar to DDR-I device with 1 cycle read latency

when DOFF is asserted LOW

■ 1.8 V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4 V–V_DD

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

❐ Supports both 1.5 V and 1.8 V IO supply

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible Test Access Port

For a complete list of related documentation, click here.

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

333 MHz

333

300 MHz

300

250 MHz Unit

250

430

530

MHz

Maximum Operating Current

× 18

× 36

520

490

640

600

Cypress Semiconductor Corporation

Document Number: 001-00437 Rev. *V

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 6, 2017

12 3 4 5 6 7...32

中文翻译

下载PDF

与CY7C1518KV18-250BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1518KV18-250BZXC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-250BZXI	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-250BZXI	INFINEON	获取价格	DDR-II CIO
CY7C1518KV18-300BZC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-300BZI	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-300BZXC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-300BZXC	INFINEON	获取价格	DDR-II CIO
CY7C1518KV18-300BZXI	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1518KV18-300BZXI	INFINEON	获取价格	DDR-II CIO
CY7C1518KV18-333BZC	CYPRESS	获取价格	72-Mbit DDR-II SRAM 2-Word Burst Architecture

与CY7C1518KV18-250BZI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1518KV18-250BZI

CY7C1518KV18-250BZI 数据手册

与CY7C1518KV18-250BZI相关器件

与CY7C1518KV18-250BZI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1518KV18-250BZI

CY7C1518KV18-250BZI 数据手册

与CY7C1518KV18-250BZI相关器件

与CY7C1518KV18-250BZI相关文章

您还可以找

您在本页遇到什么问题？