Datasheet > CY7C151*V18

CY7C151*V18

更新时间： 2024-02-20 16:21:40

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率
页数	文件大小	规格书
8页	244K
描述
RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

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CY7C151*V18 数据手册

This issue only affects the EXTEST command when the device is in the JTAG mode. The normal functionality

of the device will not be affected.

• TRIGGER CONDITION(S)

EXTEST command executed immediately after power-up without providing any K clock cycles.

• SCOPE OF IMPACT

This issue only impacts the EXTEST command when device is tested in the JTAG mode. Normal functionality

of the device is not affected.

• EXPLANATION OF ISSUE

Impedance matching circuitry (ZQ) is present on the QDR/DDR devices to set the desired impedance on the

outputs. This ZQ circuitry is updated every 1000 clock cycles of K clock to ensure that the impedance of the

O/P is set to valid state. However, when the device is operated in the JTAG mode immediately after power-

up, high frequency noise on the input K clock can be treated by the ZQ circuitry as valid clocks thereby setting

the outputs in to a high-impedance mode. If a minimum of 1000 valid K clocks are applied before performing

the JTAG test, this should clear the ZQ circuitry and ensure that the outputs are driven to valid impedance

levels.

• WORKAROUND

Elimination of the issue: After power-up, before any valid operations are performed on the device, insert a

minimum of 1000 valid clocks on K input.

• FIX STATUS

The fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the

JTAG signal. The fix has been implemented on the new revision and is now available. The new revision is an

increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and

the new revision after the fix..

Current Revision

CY7C129*DV18

CY7C130*DV25

CY7C130*BV18

CY7C130*BV25

CY7C132*BV25

CY7C131*BV18

CY7C132*BV18

CY7C139*BV18

CY7C191*BV18

CY7C141*AV18

CY7C142*AV18

CY7C151*V18

CY7C152*V18

New Revision after the Fix

CY7C129*EV18

CY7C130*EV25

CY7C130*CV18

CY7C130*CV25

CY7C132*CV25

CY7C131*CV18

CY7C132*CV18

CY7C139*CV18

CY7C191*CV18

CY7C141*BV18

CY7C142*BV18

CY7C151*AV18

CY7C152*AV18

Table 4. List of Affected devices and the new revision

Document #: 001-06217 Rev. *C

Page 6 of 8

1...3 4 567 8

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与CY7C151*V18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1510AV18	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18_07	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510AV18_09	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510AV18-167BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-167BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-167BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-167BZXI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-200BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-200BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-200BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur

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