Datasheet > CY7C151*V18

CY7C151*V18

更新时间： 2024-01-03 16:26:36

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率
页数	文件大小	规格书
8页	244K
描述
RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

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CY7C151*V18 数据手册

• ISSUE DEFINITION

This issue involves the output buffer entering an unidentified state when the input signals (only Control signals

or Clocks) are floating during reset or initialization of the memory controller after power up.

• PARAMETERS AFFECTED

No timing parameters are affected. The device may drive the outputs even though the read operation is not

enabled. A dummy read is performed to clear this condition.

• TRIGGER CONDITION(S)

Input signals(namely RPS# for QDR-I/QDRII , WE# and LD# for DDR-I/DDRII) or Clocks (K/K# and/or C/C#)

are floating during reset or initialization of the memory controller after power up.

• SCOPE OF IMPACT

This issue will jeopardize any number of writes or reads which take place after the controls or clock are left

floating. This can occur anywhere in the SRAM access ( all the way from power up of the memory device to

transitions taking place for read/write accesses to the memory device) if the above trigger conditions are met.

• EXPLANATION OF ISSUE

Figure 3 shows the output register Reset circuit with an SR Latch circled. This latch has two inputs with one

of them coming from some logic affected by the clock and RPS#(QDR) or WE# and LD#(DDR).The issue

happens when clocks are glitching/toggling with controls floating. This will cause the SR latch to be taken into

an unidentified state. The SR Latch will need to be reset by a dummy read operation if this happens.

SR LATCH

Figure 3. Output Register Reset Circuit

• WORKAROUND

This is viable only if the customer has the trigger conditions met during reset or initialization of the memory

controller after power up. In order for the workaround to perform properly, Cypress recommends the insertion

of a minimum of 16 “dummy” READ operations to every SRAM device on the board prior to writing any

meaningful data into the SRAM. After this one “dummy” READ operation, the device will perform properly.

“Dummy” READ is defined as a read operation to the device that is not meant to retrieve required data. The

“dummy” READ can be to any address location in the SRAM. Refer to Figure 4 for the dummy read implemen-

tation.

Document #: 001-06217 Rev. *C

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与CY7C151*V18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1510AV18	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18_07	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510AV18_09	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510AV18-167BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-167BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-167BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-167BZXI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-200BZC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-200BZI	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1510AV18-200BZXC	CYPRESS	获取价格	72-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur

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