50
CY7C150
1Kx4 Static RAM
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Features
• Memory reset function
• 1024x4 staticRAM for control storein high-speed com-
puters
• CMOS for optimum speed/power
• High speed
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
— 10 ns (commercial)
— 12 ns (military)
• Low power
— 495 mW (commercial)
— 550 mW (military)
• Separate inputs and outputs
• 5-voltpowersupply±10%toleranceinbothcommercial
and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible inputs and outputs
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D0−D3) is written into the memory location
specified on the address pins (A0 through A9).
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O0 through O3).
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
set feature that allows the entire memory to be reset in two
memory cycles.
A die coat is used to insure alpha immunity.
Logic Block Diagram
PinConfiguration
RS
D D D D
1 2 3
0
DIP/SOIC
Top View
CS
OE
DATAINPUT
CONTROL
A
A
4
V
A
2
3
1
2
3
4
5
24
23
22
21
20
19
18
17
16
15
14
13
CC
WE
A
A
5
1
A
6
A
0
A
0
O
0
A
RS
CS
7
A
1
A
7C150
8
6
7
8
O
1
64x64
ARRAY
A
2
A
9
D
0
WE
OE
D
3
D
O
3
O
A
3
O
2
A
4
D
9
1
10
11
12
O
0
A
5
2
O
3
O
1
GND
2
COLCUMONLDUECMONDER
DECODER
C150-2
C150–1
A
6
A
7
A
8
A
9
Selection Guide
7C150−10 7C150−12 7C150−15 7C150−25 7C150−35
Maximum Access Time (ns)
Commercial
Military
10
12
12
15
15
25
25
35
90
Maximum Operating Current (mA)
Commercial
Military
90
90
90
90
100
100
100
100
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05024 Rev. **
Revised August 24, 2001
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