Datasheet > 存储 > SRAM> CY7C1427JV18-300BZXC

CY7C1427JV18-300BZXC

更新时间： 2024-11-29 03:09:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
26页	630K
描述
36-Mbit DDR-II SRAM 2-Word Burst Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1427JV18-300BZXC 数据手册

浏览型号CY7C1427JV18-300BZXC的Datasheet PDF文件第2页

浏览型号CY7C1427JV18-300BZXC的Datasheet PDF文件第3页

浏览型号CY7C1427JV18-300BZXC的Datasheet PDF文件第4页

浏览型号CY7C1427JV18-300BZXC的Datasheet PDF文件第5页

浏览型号CY7C1427JV18-300BZXC的Datasheet PDF文件第6页

浏览型号CY7C1427JV18-300BZXC的Datasheet PDF文件第7页

CY7C1416JV18, CY7C1427JV18

CY7C1418JV18, CY7C1420JV18

36-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz clock for high bandwidth

The CY7C1416JV18, CY7C1427JV18, CY7C1418JV18 and

CY7C1420JV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K. Read data is

driven on the rising edges of C and C if provided, or on the rising

edge of K and K if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1416JV18

and two 9-bit words in the case of CY7C1427JV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1416JV18 and

CY7C1427JV18. On CY7C1418JV18 and CY7C1420JV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1418JV18 and two 36-bit words in the case of

CY7C1420JV18 sequentially into or out of the device.

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz for DDR-II

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when DLL is

enabled

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates like a DDR-I device with 1 cycle read latency in DLL

off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V_DD

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both in Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1416JV18 – 4M x 8

CY7C1427JV18 – 4M x 9

CY7C1418JV18 – 2M x 18

CY7C1420JV18 – 1M x 36

Selection Guide

Description

Maximum Operating Frequency

300 MHz

300

Unit

MHz

Maximum Operating Current

930

x18

x36

975

1010

Cypress Semiconductor Corporation

Document Number: 001-12558 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 10, 2008

[+] Feedback

12 3 4 5 6 7...26

中文翻译

下载PDF

与CY7C1427JV18-300BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1427JV18-300BZXI	CYPRESS	获取价格	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1427KV18	CYPRESS	获取价格	36-Mbit DDR II SRAM 2-Word Burst Architecture
CY7C1428AV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1428AV18-167BZI	CYPRESS	获取价格	DDR SRAM, 4MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1428AV18-167BZXC	CYPRESS	获取价格	DDR SRAM, 4MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-
CY7C1428AV18-167BZXI	CYPRESS	获取价格	DDR SRAM, 4MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-
CY7C1428AV18-200BZC	CYPRESS	获取价格	DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1428AV18-200BZI	CYPRESS	获取价格	DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1428AV18-200BZXC	CYPRESS	获取价格	DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA
CY7C1428AV18-250BZC	CYPRESS	获取价格	DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

与CY7C1427JV18-300BZXC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

39
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

63

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1427JV18-300BZXC

CY7C1427JV18-300BZXC 数据手册

与CY7C1427JV18-300BZXC相关器件

与CY7C1427JV18-300BZXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1427JV18-300BZXC

CY7C1427JV18-300BZXC 数据手册

与CY7C1427JV18-300BZXC相关器件

与CY7C1427JV18-300BZXC相关文章

您还可以找

您在本页遇到什么问题？