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CY7C1386DV25-167BZXI PDF预览

CY7C1386DV25-167BZXI

更新时间： 2024-02-14 20:52:48
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
30页 1165K
描述
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1386DV25-167BZXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.4 mm
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：13 mm
Base Number Matches：1

CY7C1386DV25-167BZXI 数据手册

 浏览型号CY7C1386DV25-167BZXI的Datasheet PDF文件第3页浏览型号CY7C1386DV25-167BZXI的Datasheet PDF文件第4页浏览型号CY7C1386DV25-167BZXI的Datasheet PDF文件第5页浏览型号CY7C1386DV25-167BZXI的Datasheet PDF文件第7页浏览型号CY7C1386DV25-167BZXI的Datasheet PDF文件第8页浏览型号CY7C1386DV25-167BZXI的Datasheet PDF文件第9页 
CY7C1386DV25, CY7C1386FV25  
CY7C1387DV25, CY7C1387FV25  
Pin Definitions  
Name  
IO  
Description  
A0, A1, A  
Input-  
Synchronous  
Address inputs used to select one of the address locations. Sampled at the  
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3  
[2]  
are sampled active. A1: A0 are fed to the two-bit counter.  
.
BWA, BWB  
BWC, BWD  
Input-  
Synchronous  
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes  
to the SRAM. Sampled on the rising edge of CLK.  
GW  
Input-  
Synchronous  
Global write enable input, active LOW. When asserted LOW on the rising edge  
of CLK, a global write is conducted (all bytes are written, regardless of the values  
on BWX and BWE).  
BWE  
CLK  
CE1  
Input-  
Synchronous  
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This  
signal must be asserted LOW to conduct a byte write.  
Input-  
Clock  
Clock input. Used to capture all synchronous inputs to the device. Also used to  
increment the burst counter when ADV is asserted LOW, during a burst operation.  
Input-  
Synchronous  
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in  
conjunction with CE2 and CE3 [2] to select or deselect the device. ADSP is ignored  
if CE1 is HIGH. CE1 is sampled only when a new external address is loaded.  
[2]  
CE2  
Input-  
Synchronous  
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in  
conjunction with CE1 and CE3 [2] to select or deselect the device. CE2 is sampled  
only when a new external address is loaded.  
[2]  
CE3  
Input-  
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in  
Synchronous  
conjunction with CE1 and CE2 [t2o] select or deselect the device. Not connected for  
BGA. Where referenced, CE3  
is assumed active throughout this document for  
BGA. CE3 is sampled only when a new external address is loaded.  
OE  
Input-  
Output enable, asynchronous input, active LOW. Controls the direction of the  
Asynchronous IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ  
pins are tri-stated, and act as input data pins. OE is masked during the first clock  
of a read cycle when emerging from a deselected state.  
ADV  
Input-  
Advance input signal, sampled on the rising edge of CLK, active LOW. When  
Synchronous  
asserted, it automatically increments the address in a burst cycle.  
ADSP  
Input-  
Synchronous  
Address strobe from processor, sampled on the rising edge of CLK, active  
LOW. When asserted LOW, addresses presented to the device are captured in the  
address registers. A1: A0 are also loaded into the burst counter. When ADSP and  
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is  
deasserted HIGH.  
ADSC  
Input-  
Synchronous  
Address strobe from controller, sampled on the rising edge of CLK, active  
LOW. When asserted LOW, addresses presented to the device are captured in the  
address registers. A1: A0 are also loaded into the burst counter. When ADSP and  
ADSC are both asserted, only ADSP is recognized.  
ZZ  
Input-  
ZZ sleep input, active HIGH. When asserted HIGH places the device in a  
Asynchronous non-time-critical sleep condition with data integrity preserved. For normal operation,  
this pin has to be LOW or left floating. ZZ pin has an internal pull down.  
IO-  
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that  
is triggered by the rising edge of CLK. As outputs, they deliver the data contained  
in the memory location specified by the addresses presented during the previous  
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE  
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are  
placed in a tri-state condition.  
DQs, DQPs  
Synchronous  
VDD  
Power Supply Power supply inputs to the core of the device.  
Document Number: 38-05548 Rev. *E  
Page 6 of 30  
1...3456789...30

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