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CY7C1386D-200AI PDF预览

CY7C1386D-200AI

更新时间： 2024-02-15 21:35:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
29页 464K
描述
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

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CY7C1386D-200AI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
针数：165Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.53最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.07 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：13 mmBase Number Matches：1

CY7C1386D-200AI 数据手册

 浏览型号CY7C1386D-200AI的Datasheet PDF文件第3页浏览型号CY7C1386D-200AI的Datasheet PDF文件第4页浏览型号CY7C1386D-200AI的Datasheet PDF文件第5页浏览型号CY7C1386D-200AI的Datasheet PDF文件第7页浏览型号CY7C1386D-200AI的Datasheet PDF文件第8页浏览型号CY7C1386D-200AI的Datasheet PDF文件第9页 
PRELIMINARY  
CY7C1386D  
CY7C1387D  
Pin Definitions  
Name  
I/O  
Description  
Address Inputs used to select one of the address locations. Sampled at the  
A0, A1, A  
Input-  
[2]  
Synchronous  
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3  
are sampled active. A1: A0 are fed to the two-bit counter.  
.
BWA, BWB  
BWC, BWD  
Input-  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes  
Synchronous  
to the SRAM. Sampled on the rising edge of CLK.  
GW  
Input-  
Global Write Enable Input, active LOW. When asserted LOW on the rising edge  
of CLK, a global write is conducted (ALL bytes are written, regardless of the values  
on BWX and BWE).  
Synchronous  
BWE  
CLK  
CE1  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This  
Synchronous  
signal must be asserted LOW to conduct a byte write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used to  
increment the burst counter when ADV is asserted LOW, during a burst operation.  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in  
conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if  
CE1 is HIGH. CE1 is sampled only when a new external address is loaded.  
Synchronous  
[2]  
CE2  
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in  
conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only  
when a new external address is loaded.  
Synchronous  
[2]  
CE3  
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in  
Synchronous  
conjunction with CE andCE to select/deselect the device.  
Not connected for BGA.  
1
Where referenced, CE3[2] is2assumed active throughout this document for BGA.  
CE3 is sampled only when a new external address is loaded.  
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the  
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ  
pins are tri-stated, and act as input data pins. OE is masked during the first clock of  
a read cycle when emerging from a deselected state.  
Asynchronous  
ADV  
Input-  
Advance Input signal, sampled on the rising edge of CLK, active LOW. When  
Synchronous  
asserted, it automatically increments the address in a burst cycle.  
ADSP  
Input-  
Address Strobe from Processor, sampled on the rising edge of CLK, active  
LOW. When asserted LOW, addresses presented to the device are captured in the  
address registers. A1: A0 are also loaded into the burst counter. When ADSP and  
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is  
deasserted HIGH.  
Synchronous  
ADSC  
Input-  
Address Strobe from Controller, sampled on the rising edge of CLK, active  
LOW. When asserted LOW, addresses presented to the device are captured in the  
address registers. A1: A0 are also loaded into the burst counter. When ADSP and  
ADSC are both asserted, only ADSP is recognized.  
Synchronous  
ZZ  
Input-  
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a  
non-time-critical “sleep” condition with data integrity preserved. For normal  
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.  
Asynchronous  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that  
is triggered by the rising edge of CLK. As outputs, they deliver the data contained  
in the memory location specified by the addresses presented during the previous  
DQs, DQPX  
Synchronous  
cycle. The direction of the pins is controlled by OE. When OE  
clock rise of the read  
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are  
placed in a tri-state condition.  
VDD  
VSS  
Power Supply  
Ground  
Power supply inputs to the core of the device.  
Ground for the core of the device.  
Ground for the I/O circuitry.  
VSSQ  
I/O Ground  
Document #: 38-05545 Rev. *A  
Page 6 of 30  
1...3456789...29

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