Datasheet > CY7C1381D

CY7C1381D

更新时间： 2024-11-29 05:19:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	466K
描述
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1381D 数据手册

CY7C1381D

CY7C1383D

PRELIMINARY

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 512K × 36/1M × 18 common I/O

• 3.3V –5% and +10% core power supply (V_DD

The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit

18 Synchronous Flow-through SRAMs, respectively

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

)

• 2.5V or 3.3V I/O supply (V_DDQ

• Fast clock-to-output time

— 6.5 ns (133-MHz version)

— 8.5 ns (100-MHz version)

)

addresses, all data inputs, address-pipelining Chip Enable

[2]

• Provide high-performance 2-1-1-1 access rate

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

• User-selectable burst counter supporting Intel^

Control inputs (

), Write Enables

(

ADV

BW_x

and

ADSC ADSP

Pentium^interleaved or linear burst sequences

), and Global Write (

BWE

). Asynchronous

and

inputs

(

)

and the ZZ pin

include the Output Enable

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

The CY7C1381D/CY7C1383D allows either interleaved or

linear burst sequences, selected by the MODE input pin. A

HIGH selects an interleaved burst sequence, while a LOW

selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

• Offered in JEDEC-standard lead-free 100-pin TQFP

,119-ball BGA and 165-ball fBGA packages

• JTAG boundary scan for BGA and fBGA packages

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

The CY7C1381D/CY7C1383D operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

210

175

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05544 Rev. *A

Revised November 2, 2004

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1381D相关器件

型号	品牌	获取价格	描述	数据表
CY7C1381D_07	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D_11	CYPRESS	获取价格	18 Mbit (512 K × 36/1 M × 18) Flow Through SR
CY7C1381D_13	CYPRESS	获取价格	18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1381D-100AXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100AXCT	CYPRESS	获取价格	Standard SRAM, 512KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLAST
CY7C1381D-100AXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100BGCT	CYPRESS	获取价格	Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1381D-100BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100BGIT	CYPRESS	获取价格	Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119

与CY7C1381D相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

39
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

63

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1381D

CY7C1381D 数据手册

与CY7C1381D相关器件

与CY7C1381D相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1381D

CY7C1381D 数据手册

与CY7C1381D相关器件

与CY7C1381D相关文章

您还可以找

您在本页遇到什么问题？