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CY7C1360A-150BGI PDF预览

CY7C1360A-150BGI

更新时间： 2024-02-05 06:41:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器
页数 文件大小 规格书
28页 559K
描述
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

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中文翻译

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CY7C1360A-150BGI 技术参数

生命周期：Contact Manufacturer包装说明：BGA,
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.68
最长访问时间：4.5 ns其他特性：PIPELINE ARCHITECTURE
JESD-30 代码：R-PBGA-B119长度：22 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：119字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX36封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
座面最大高度：2.4 mm最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
宽度：14 mmBase Number Matches：1

CY7C1360A-150BGI 数据手册

 浏览型号CY7C1360A-150BGI的Datasheet PDF文件第3页浏览型号CY7C1360A-150BGI的Datasheet PDF文件第4页浏览型号CY7C1360A-150BGI的Datasheet PDF文件第5页浏览型号CY7C1360A-150BGI的Datasheet PDF文件第7页浏览型号CY7C1360A-150BGI的Datasheet PDF文件第8页浏览型号CY7C1360A-150BGI的Datasheet PDF文件第9页 
CY7C1360A  
CY7C1362A  
256K × 36 Pin Descriptions (continued)  
X36 PBGA Pins  
(a) 6P, 7P, 7N, 6N, 6M, (a) 51, 52, 53, 56, DQa  
6L, 7L, 6K, 7K, 57, 58, 59, 62, 63 DQb  
(b) 7H, 6H, 7G, 6G, 6F, (b) 68, 69, 72, 73, DQc  
6E, 7E, 7D, 6D, 74, 75, 78, 79, 80 DQd  
(c) 2D, 1D, 1E, 2E, 2F, (c) 1, 2, 3, 6, 7, 8, 9,  
1G, 2G, 1H, 2H, 12, 13  
(d) 1K, 2K, 1L, 2L, 2M, (d) 18, 19, 22, 23,  
X36 QFP Pins  
Name  
Type  
Description  
Input/  
Output  
Data Inputs/Outputs: First Byte is DQa. Second Byte is  
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data  
must meet set-up and hold times around the rising edge  
of CLK.  
1N, 2N, 1P, 2P  
24, 25, 28, 29, 30  
2U  
3U  
4U  
38  
39  
43  
TMS  
TDI  
TCK  
Input  
IEEE 1149.1 test inputs. LVTTL-level inputs. Not  
available for TA/A package version.  
for BG/B and T/AJ  
version  
5U  
42  
TDO  
VCC  
Output  
IEEE 1149.1 test output. LVTTL-level output. Not  
available for TA package version.  
for BG/B and T/AJ  
version  
4C, 2J, 4J, 6J, 4R  
15, 41, 65, 91  
Power Supply Core power supply: +3.3V –5% and +10%  
3D, 5D, 3E, 5E, 3F, 5F, 5, 10, 17, 21, 26, VSS  
3H, 5H, 3K, 5K, 3M, 40, 55, 60, 67, 71,  
Ground  
Ground: GND.  
5M, 3N, 5N, 3P, 5P  
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,  
1M, 7M, 1U, 7U 61, 70, 77  
76, 90  
VCCQ  
NC  
I/O Power  
Supply  
Power Supply for the I/O circuitry  
1B,7B,1C,7C,4D,3J, 14, 16, 66  
-
No Connect: These signals are not internally connected.  
5J, 4L, 1R, 5R, 7R, 1T, 38, 39, 42 for TA/A  
User can leave it floating or connect it to VCC or VSS.  
2T, 6T, 6U  
version  
512K × 18 Pin Descriptions  
X18 PBGA Pins  
4P  
4N  
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32, 100, A  
5B, 6B, 2C, 3C, 5C, 99, 82, 81, 80, 48,  
6C,2R,6R,2T,3T,5T, 47, 46, 45, 44, 49,  
X18 QFP Pins  
Name  
Type  
Description  
37  
36  
A0  
A1  
Input-  
Addresses: These inputs are registered and must meet  
Synchronous the set up and hold times around the rising edge of CLK.  
The burst counter generates internal addresses  
associated with A0 and A1, during burst cycle and wait  
cycle.  
6T  
50  
92 (T/AJ Version)  
43 (TA/A Version)  
5L  
3G  
93  
94  
BWa  
BWb  
Input-  
Byte Write Enables: A byte Write enable is LOW for a  
Synchronous WritecycleandHIGHfor aReadcycle. BWacontrolsDQa.  
BWb controls DQb. Data I/O are high impedance if either  
of these inputs are LOW, conditioned by BWE being LOW.  
4M  
4H  
87  
88  
BWE  
GW  
Input-  
Write Enable: This active LOW input gates byte Write  
Synchronous operations and must meet the set-up and hold times  
around the rising edge of CLK.  
Input-  
Global Write: This active LOW input allows a full 18-bit  
Synchronous Write to occur independent of the BWE and WEn lines and  
must meet the set-up and hold times around the rising  
edge of CLK.  
4K  
89  
CLK  
Input-  
Clock: This signal registers the addresses, data, chip  
Synchronous enables, Write control and burst control inputs on its rising  
edge. All synchronous inputs must meet set-up and hold  
times around the clock’s rising edge.  
4E  
2B  
98  
97  
CE  
Input-  
Chip Enable: This active LOW input is used to enable the  
Synchronous device and to gate ADSP.  
CE2  
Input-  
Synchronous device.  
Chip Enable: This active HIGH input is used to enable the  
Document #: 38-05258 Rev. *A  
Page 6 of 28  
1...3456789...28

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与CY7C1360A-150BGI相关器件

型号 品牌 描述 获取价格 数据表
CY7C1360A-166AC CYPRESS 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

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CY7C1360A-166AC ROCHESTER Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1360A-166ACT CYPRESS Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1360A-166AI CYPRESS 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

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CY7C1360A-166AJC CYPRESS 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

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CY7C1360A-166AJC ROCHESTER Standard SRAM, 256KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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