Datasheet > CY7C1360A-166AJC

CY7C1360A-166AJC

更新时间： 2024-02-09 22:12:18

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		时钟静态存储器内存集成电路
页数	文件大小	规格书
28页	561K
描述
Standard SRAM, 256KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1360A-166AJC 技术参数

生命周期：	Contact Manufacturer	包装说明：	LQFP,
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.68
最长访问时间：	4 ns	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	36
功能数量：	1	端子数量：	100
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256KX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

CY7C1360A-166AJC 数据手册

CY7C1360A

CY7C1362A

256K x 36/512K x 18 Synchronous

Pipelined Burst SRAM

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), depth-expansion

Chip Enables (CE₂and CE₃), burst control inputs (ADSC,

ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and

BWE), and global Write (GW). However, the CE₃chip enable

input is only available for the TA package version.

Features

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 225, 200, 166, and 150 MHz

• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Optimal for depth expansion (one cycle chip deselect

to eliminate bus contention)

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V-tolerant inputs except I/Os

• Clamp diodes to V_SSat all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion:

three chip enables for A package version and two chip

enables for BG and AJ package versions

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

• Address pipeline capability

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down feature available using ZZ

mode or CE deselect

• JTAG boundary scan for BG and AJ package version

• Low-profile119-bump,14-mm×22-mmPBGA(BallGrid

Array) and 100-pin TQFP packages

Address, data inputs, and Write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the Write control inputs.

Individual byte Write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

For the BGA and TQFP AJ package versions, four pins are

used to implement JTAG test capabilities: Test Mode Select

(TMS), Test Data-In (TDI), Test Clock (TCK), and Test

Data-Out (TDO). The JTAG circuitry is used to serially shift

data to and from the device. JTAG inputs use LVTTL/LVCMOS

levels to shift data during this testing mode of operation. The

TA package version does not offer the JTAG capability.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1360A and CY7C1362A operate from a +3.3V

power supply. All inputs and outputs are LVTTL-compatible.

The CY7C1360A and CY7C1362A SRAMs integrate 262,144

36 and 524,288 × 18 SRAM cells with advanced

Selection Guide

7C1360A-225

7C1362A-225

7C1360A-200

7C1362A-200

7C1360A-166

7C1362A-166

7C1360A-150

7C1362A-150

Unit

Maximum Access Time

2.5

650

3.0

600

3.5

520

3.5

460

Maximum Operating Current

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05258 Rev. *C

Revised January 18, 2003

12 3 4 5 6 7...28

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与CY7C1360A-166AJC相关器件

型号	品牌	描述	获取价格	数据表
CY7C1360A-166AJI	CYPRESS	256K x 36/512K x 18 Synchronous Pipelined Burst SRAM	获取价格
CY7C1360A-166BGC	CYPRESS	256K x 36/512K x 18 Synchronous Pipelined Burst SRAM	获取价格
CY7C1360A-166BGCT	CYPRESS	Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	获取价格
CY7C1360A-166BGI	CYPRESS	256K x 36/512K x 18 Synchronous Pipelined Burst SRAM	获取价格
CY7C1360A-166BGI	ROCHESTER	Cache SRAM, 256KX36, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119	获取价格
CY7C1360A-200AC	CYPRESS	256K x 36/512K x 18 Synchronous Pipelined Burst SRAM	获取价格

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