Datasheet > 存储 > SRAM> CY7C1359A-133AC

CY7C1359A-133AC

更新时间： 2024-01-23 00:38:48

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器
页数	文件大小	规格书
24页	234K
描述
256K x 18 Synchronous-Pipelined Cache Tag RAM

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技术参数
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CY7C1359A-133AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.88	最长访问时间：	4 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE TAG SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.06 A
子类别：	SRAMs	最大压摆率：	0.25 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

CY7C1359A-133AC 数据手册

327

CY7C1359A/GVT71256T18

256K x 18 Synchronous-Pipelined Cache Tag RAM

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

Features

• Fast match times: 3.5, 3.8, 4.0 and 4.5 ns

• Fast clock speed: 166, 150, 133, and 100 MHz

• Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns

• Pipelined data comparator

• Data input register load control by DEN

• Optimal for depth expansion (one cycle chip deselect

to eliminate bus contention)

• 3.3V –5% and +10% core power supply

• 2.5V or 3.3V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V_SSat all inputs and outputs

• Common data inputs and data outputs

• JTAG boundary scan

inputs include all addresses, all data inputs, address-pipelin-

ing Chip Enable (CE), depth-expansion Chip Enables (CE₂

and CE₂), Burst Control Inputs (ADSC, ADSP, and ADV), Write

Enables (WEL, WEH, and BWE), Global Write (GW), and Data

Input Enable (DEN).

Asynchronous inputs include the Burst Mode Control (MODE),

the Output Enable (OE) and the Match Output Enable (MOE).

The data outputs (Q) and Match Output (MATCH), enabled by

OE and MOE respectively, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

Data inputs are registered with Data Input Enable (DEN) and

chip enable pins (CE, CE₂, and CE₂). The outputs of the data

input registers are compared with data in the memory array

and a match signal is generated. The match output is gated

into a pipeline register and released to the match output pin at

the next rising edge of Clock (CLK).

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address

pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to two bytes wide as controlled by the write control inputs. In-

dividual byte write allows individual byte to be written. WEL

controls DQ1–DQ9. WEH controls DQ10–DQ18. WEL and

WEH can be active only with BWE being LOW. GW being LOW

causes all bytes to be written.

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• Low-profile JEDEC standard 100-pin TQFP package

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high valued

resistors.

The CY7C1359C/GVT71256T18 operates from a +3.3V pow-

er supply with output power supply being +2.5V or +3.3V. All

inputs and outputs are LVTTL compatible. The device is ideally

suited for address tag RAM for up to 8 MB secondary cache.

Selection Guide

7C1359A-166

71256T36-6

7C1359A-150

71256T36-6.7

7C1359A-133

71256T36-7.5

7C1359A-100

71256T36-10

Maximum Access Time (ns)

3.5

310

3.8

275

4.0

250

4.5

190

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Cypress Semiconductor Corporation

Document #: 38-05120 Rev. **

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised September 13, 2001

12 3 4 5 6 7...24

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