Datasheet > CY7C1356V25-166AC

CY7C1356V25-166AC

更新时间： 2024-11-20 05:46:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	722K
描述
ZBT SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1356V25-166AC 数据手册

浏览型号CY7C1356V25-166AC的Datasheet PDF文件第2页

浏览型号CY7C1356V25-166AC的Datasheet PDF文件第3页

浏览型号CY7C1356V25-166AC的Datasheet PDF文件第4页

浏览型号CY7C1356V25-166AC的Datasheet PDF文件第5页

浏览型号CY7C1356V25-166AC的Datasheet PDF文件第6页

356V25

CY7C1354V25

CY7C1356V25

PRELIMINARY

256Kx36/512Kx18 Pipelined SRAM with NoBL™ Architecture

spectively. They are designed specifically to support unlimited

Features

true back-to-back Read/Write operations without the insertion

of wait states. The CY7C1354V25/CY7C1356V25 is equipped

with the advanced No Bus Latency™ (NoBL™) logic required

to enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically im-

proves the throughput of data through the SRAM, especially in

systems that require frequent Write/Read transitions. The

CY7C1354V25/CY7C1356V25 is pin compatible and function-

ally equivalent to ZBT devices.

• Pin compatible and functionally equivalent to ZBT™

• Supports 200-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully Registered (inputs and outputs) for pipelined op-

eration

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal, which

when deasserted suspends operation and extends the previ-

ous clock cycle. Maximum access delay from the clock rise is

3.2 ns (200-MHz device).

• Common I/O architecture

• Single 2.5V power supply

• Fast clock-to-output times

— 3.2 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.2 ns (for 133-MHz device)

Write operations are controlled by the Byte Write Selects

(BWS_a–BWS_dfor CY7C1354V25 and BWS_a–BWS_bfor

CY7C1356V25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

— 5.0 ns (for 100-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in 100 TQFP & 119 BGA Packages

• Burst Capability—linear or interleaved burst order

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Functional Description

The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36

and 512K by 18 Synchronous-Pipelined Burst SRAMs, re-

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and WRITE

LOGIC

256KX36/

512KX18

MEMORY

ARRAY

CY7C1354 CY7C1356

X = 17:0 X = 18:0

BWS

Mode

X = a, b, c, d X = a, b

BWS

Selection Guide

7C1354V25-200 7C1354V25-166 7C1354V25-133 7C1354V25-100

7C1356V25-200 7C1356V25-166 7C1356V25-133 7C1356V25-100

Maximum Access Time (ns)

3.2

475

3.5

450

4.0

370

5.0

300

Maximum Operating Current (mA)

Com’l

Maximum CMOS Standby Current (mA) Com’l

Shaded areas contain advance information.

No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05263 Rev. **

Revised March 6, 2002

12 3 4 5 6 7...27

中文翻译

下载PDF

与CY7C1356V25-166AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1357A	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1357A-100AC	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1357A-100AC	ROCHESTER	获取价格	512KX18 ZBT SRAM, 7.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1357A-100AI	CYPRESS	获取价格	256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture
CY7C1357A-100BGC	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1357A-100BGI	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1357A1-100AC	CYPRESS	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1357A1-100BGI	CYPRESS	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1357A-117AC	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1357A-117BGC	CYPRESS	获取价格	ZBT SRAM, 512KX18, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

与CY7C1356V25-166AC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

44

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1356V25-166AC

CY7C1356V25-166AC 数据手册

与CY7C1356V25-166AC相关器件

与CY7C1356V25-166AC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1356V25-166AC

CY7C1356V25-166AC 数据手册

与CY7C1356V25-166AC相关器件

与CY7C1356V25-166AC相关文章

您还可以找

您在本页遇到什么问题？