Datasheet > CY7C11571KV18

CY7C11571KV18

更新时间： 2022-10-24 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
29页	850K
描述
18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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数据手册

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CY7C11571KV18 数据手册

CY7C11461KV18, CY7C11571KV18

CY7C11481KV18, CY7C11501KV18

Logic Block Diagram (CY7C11461KV18)

Write

Reg

Write

Reg

(19:0)

Address

Output

R/W

CLK

Logic

Gen.

Control

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

R/W

NWS

[1:0]

[7:0]

QVLD

Logic Block Diagram (CY7C11571KV18)

Write

Reg

Write

Reg

(19:0)

Address

Output

Logic

Control

CLK

R/W

Gen.

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

R/W

BWS

[0]

[8:0]

QVLD

Note

1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V

= 1.4V to V

DDQ

Document Number: 001-53198 Rev. *F

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与CY7C11571KV18相关器件

型号	品牌	描述	获取价格	数据表
CY7C1157KV18	CYPRESS	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)	获取价格
CY7C1157V18	CYPRESS	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)	获取价格
CY7C1157V18-300BZC	CYPRESS	DDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	获取价格
CY7C1157V18-300BZXC	CYPRESS	DDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA	获取价格
CY7C1157V18-300BZXI	CYPRESS	DDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA	获取价格
CY7C1157V18-333BZC	CYPRESS	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)	获取价格