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CY7C1041BV33-25VC PDF预览

CY7C1041BV33-25VC

更新时间: 2024-01-24 18:40:55
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 190K
描述
Standard SRAM, 256KX16, 25ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44

CY7C1041BV33-25VC 技术参数

生命周期:Contact Manufacturer包装说明:SOJ,
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.6
Is Samacsys:N最长访问时间:25 ns
JESD-30 代码:R-PDSO-J44长度:28.575 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:44字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX16封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
座面最大高度:3.7592 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

CY7C1041BV33-25VC 数据手册

 浏览型号CY7C1041BV33-25VC的Datasheet PDF文件第2页浏览型号CY7C1041BV33-25VC的Datasheet PDF文件第3页浏览型号CY7C1041BV33-25VC的Datasheet PDF文件第4页浏览型号CY7C1041BV33-25VC的Datasheet PDF文件第5页浏览型号CY7C1041BV33-25VC的Datasheet PDF文件第6页浏览型号CY7C1041BV33-25VC的Datasheet PDF文件第7页 
041BV33  
CY7C1041BV33  
256K x 16 Static RAM  
written into the location specified on the address pins (A0  
through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
Features  
• High speed  
— tAA = 12 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Low active power  
— 612 mW (max.)  
• Low CMOS standby power (Commercial L version)  
— 1.8 mW (max.)  
• 2.0V Data Retention (600 µW at 2.0V retention)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Functional Description  
The CY7C1041BV33 is a high-performance CMOS Static  
RAM organized as 262,144 words by 16 bits.  
The CY7C1041BV33 is available in a standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
Logic Block Diagram  
Pin Configuration  
SOJ  
TSOP II  
Top View  
INPUT BUFFER  
A
0
44  
1
A
A
A
A
OE  
BHE  
BLE  
I/O  
I/O  
I/O  
0
17  
16  
15  
A
43  
42  
41  
40  
39  
38  
1
A
2
3
4
5
6
1
A
2
A
2
I/O – I/O  
256K x 16  
ARRAY  
0
7
A
3
4
A
3
A
A
4
1024 x 4096  
A
I/O I/O  
5
6
8
15  
CE  
A
I/O  
7
0
15  
A
7
8
37  
36  
35  
34  
33  
I/O  
I/O  
8
1
2
14  
13  
12  
A
9
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
COLUMN  
DECODER  
V
V
CC  
32  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
NC  
9
8
WE 17  
BHE  
18  
27  
26  
25  
A
14  
A
5
WE  
CE  
OE  
19  
A
6
A
13  
A
20  
21  
22  
A
7
12  
A
BLE  
A
24  
23  
11  
8
9
A
A
10  
Selection Guide  
-12  
12  
190  
-
-15  
-17  
17  
-20  
20  
-25  
25  
Maximum Access Time (ns)  
Maximum Operating Current (mA) Comml  
Indl  
15  
170  
190  
8
160  
180  
8
150  
170  
8
130  
150  
8
Maximum CMOS Standby  
Current (mA)  
Coml/Indl  
Coml  
8
L
0.5  
0.5  
0.5  
0.5  
0.5  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05168 Rev. **  
Revised November 15, 2001  

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