Datasheet > CY7C09379

CY7C09379

更新时间： 2022-02-02 04:53:18

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	344K
描述
32K/64K X 16/18 Synchronous Dual Port Static RAM

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CY7C09379 数据手册

CY7C09279/89

CY7C09379/89

Pin Definitions

Left Port

A_0L–A_15L

ADS_L

Right Port

Description

A_0R–A_15R

Address Inputs (A₀–A₁₄for 32K, A₀–A₁₅for 64K devices).

ADS_R

Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to

access the part using an externally supplied address. Asserting this signal LOW also loads the

burst counter with the address present on the address pins.

CE_0L,CE_1L

CE_0R,CE_1R

Chip Enable Input. To select either the left or right port, both CE₀AND CE₁must be asserted

to their active states (CE₀≤ V_ILand CE₁≥ V_IH).

CLK_L

CLK_R

Clock Signal. This input can be free running or strobed. Maximum clock input rate is f_MAX.

CNTEN_L

CNTEN_R

Counter Enable Input. Asserting this signal LOW increments the burst address counter of its

respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted

LOW.

CNTRST_L

CNTRST_R

Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-

tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.

I/O_0L–I/O_17L

I/O_0R–I/O_17RData Bus Input/Output (I/O₀–I/O₁₅for x16 devices).

LB_L

LB_R

Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the

lower byte. (I/O₀–I/O₈for x18, I/O₀–I/O₇for x16) of the memory array. For read operations both

the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.

UB_L

OE_L

UB_R

OE_R

Upper Byte Select Input. Same function as LB, but to the upper byte (I/O_8/9L–I/O_15/17L).

Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read

operations.

R/W_L

R/W_R

Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.

For read operations, assert this pin HIGH.

FT/PIPE_L

FT/PIPE_R

Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.

For pipelined mode operation, assert this pin HIGH.

GND

Ground Input.

No Connect.

Power Input.

V_CC

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ........................................... >1100V

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current..................................................... >200 mA

Storage Temperature................................. –65°C to +150°C

Ambient Temperature with Power Applied..–55°C to +125°C

Supply Voltage to Ground Potential............... –0.3V to +7.0V

Operating Range

Ambient

Range

Commercial

Industrial^[9]

Temperature

0°C to +70°C

–40°C to +85°C

V_CC

DC Voltage Applied to

Outputs in High Z State ................................. –0.5V to +7.0V

5V ± 10%

DC Input Voltage............................................ –0.5V to +7.0V

Note:

9. Industrial parts are available in CY7C09289 and Cy7C09389 only

Document #: 38-06040 Rev. **

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与CY7C09379相关器件

型号	品牌	获取价格	描述	数据表
CY7C09379-10AI	CYPRESS	获取价格	Multi-Port SRAM, 64KX9, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C09379-12AC	CYPRESS	获取价格	32K/64K X 16/18 Synchronous Dual Port Static RAM
CY7C09379-12AI	CYPRESS	获取价格	Dual-Port SRAM, 32KX18, 12ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C09379-6AC	CYPRESS	获取价格	32K/64K X 16/18 Synchronous Dual Port Static RAM
CY7C09379-7AC	CYPRESS	获取价格	32K/64K X 16/18 Synchronous Dual Port Static RAM
CY7C09379-9AC	CYPRESS	获取价格	32K/64K X 16/18 Synchronous Dual Port Static RAM
CY7C09379V	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09379V-10AC	CYPRESS	获取价格	Multi-Port SRAM, 64KX9, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C09379V-12AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09379V-12AC	ROCHESTER	获取价格	32KX18 DUAL-PORT SRAM, 12ns, PQFP100, PLASTIC, MS-026, TQFP-100

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