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CY62128BLL-70ZXC PDF预览

CY62128BLL-70ZXC

更新时间: 2024-09-29 22:08:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 341K
描述
128K x 8 Static RAM

CY62128BLL-70ZXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP1包装说明:8 X 20 MM, TSOP1-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.07最长访问时间:70 ns
JESD-30 代码:R-PDSO-G32JESD-609代码:e3
长度:18.4 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:8 mmBase Number Matches:1

CY62128BLL-70ZXC 数据手册

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CY62128B  
MoBL  
128K x 8 Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62128B is a high-performance CMOS static RAM  
organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE1),  
an active HIGH Chip Enable (CE2), an active LOW Output  
Enable (OE), and three-state drivers. This device has an  
automatic power-down feature that reduces power  
consumption by more than 75% when deselected.  
Writing to the device is accomplished by taking Chip Enable  
One (CE1) and Write Enable (WE) inputs LOW and Chip  
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A16).  
Reading from the device is accomplished by taking Chip  
Enable One (CE1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• 4.5V – 5.5V operation  
• CMOS for optimum speed/power  
• Low active power  
(70 ns, LL version, Commercial, Industrial)  
— 82.5 mW (max.) (15 mA)  
• Low standby power  
(70 ns, LL version, Commercial, Industrial)  
— 110 µW (max.) (15 µA)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and OE options  
The CY62128B is available in a standard 450-mil-wide SOIC,  
32-pin TSOP type I and STSOP packages.  
Logic Block Diagram  
I/O  
0
INPUT BUFFER  
I/O  
I/O  
1
2
A
A
A
0
1
2
A
A
3
4
I/O  
I/O  
I/O  
3
4
5
512x256x8  
ARRAY  
A
5
A
6
A
A
7
8
I/O  
I/O  
6
7
POWER  
DOWN  
COLUMN  
CE  
CE  
WE  
1
2
DECODER  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05300 Rev. *C  
Revised February 14, 2005  

CY62128BLL-70ZXC 替代型号

型号 品牌 替代类型 描述 数据表
CY62128BNLL-70ZXA CYPRESS

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