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CY62128BN_09

更新时间： 2024-09-30 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 585K
描述
1-Mbit (128K x 8) Static RAM

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CY62128BN_09 数据手册

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CY62128BN  
MoBL®  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62128BN is a high-performance CMOS static RAM  
organized as 128K words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE1), an active  
HIGH Chip Enable (CE2), an active LOW Output Enable (OE),  
and tri-state drivers. This device has an automatic  
power-down feature that reduces power consumption by more  
than 75% when deselected.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• 4.5V–5.5V operation  
Writing to the device is accomplished by taking Chip Enable  
One (CE1) and Write Enable (WE) inputs LOW and Chip  
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A16).  
• CMOS for optimum speed/power  
• Low active power  
(70 ns Commercial, Industrial, Automotive-A)  
— 82.5 mW (max.) (15 mA)  
Reading from the device is accomplished by taking Chip  
Enable One (CE1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
• Low standby power  
(55/70 ns Commercial, Industrial, Automotive-A)  
— 110 µW (max.) (15 µA)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and OE options  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
• Available in Pb-free and non-Pb-free 32-pin (450  
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I  
Logic Block Diagram  
Pin Configuration  
Top View  
SOIC  
V
NC  
A
16  
32  
1
2
3
4
5
CC  
31  
30  
A
15  
CE  
A
14  
2
A
12  
29  
28  
27  
26  
I/O  
WE  
A
13  
0
INPUT BUFFER  
A
7
6
A
A
I/O  
I/O  
6
8
1
2
A
A
A
0
1
2
7
8
9
10  
11  
12  
13  
14  
A
5
A
9
A
11  
OE  
25  
24  
23  
22  
21  
20  
19  
A
4
A
3
A
A
A
A
A
A
3
4
5
6
7
8
A
A
I/O  
I/O  
I/O  
2
128K x 8  
ARRAY  
10  
3
4
5
A
CE  
1
I/O  
I/O  
6
I/O  
5
1
A
7
0
I/O  
0
I/O  
1
15  
I/O  
GN  
G
GgNncD  
18  
17  
I/O  
I/O  
3
2
4
16  
I/O  
I/O  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
CE  
WE  
1
2
OE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06498 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
[+] Feedback  
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