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CY62128BNLL-55SC PDF预览

CY62128BNLL-55SC

更新时间: 2024-09-30 03:46:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
12页 594K
描述
1-Mbit (128K x 8) Static RAM

CY62128BNLL-55SC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.450 INCH, SOIC-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.25最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e0长度:20.4465 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.56
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:2.997 mm最大待机电流:0.000015 A
子类别:SRAMs最大压摆率:0.02 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:11.303 mm
Base Number Matches:1

CY62128BNLL-55SC 数据手册

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CY62128BN  
MoBL®  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62128BN is a high-performance CMOS static RAM  
organized as 128K words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE1), an active  
HIGH Chip Enable (CE2), an active LOW Output Enable (OE),  
and tri-state drivers. This device has an automatic  
power-down feature that reduces power consumption by more  
than 75% when deselected.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• 4.5V–5.5V operation  
Writing to the device is accomplished by taking Chip Enable  
One (CE1) and Write Enable (WE) inputs LOW and Chip  
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A16).  
• CMOS for optimum speed/power  
• Low active power  
(70 ns Commercial, Industrial, Automotive-A)  
— 82.5 mW (max.) (15 mA)  
Reading from the device is accomplished by taking Chip  
Enable One (CE1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
• Low standby power  
(55/70 ns Commercial, Industrial, Automotive-A)  
— 110 µW (max.) (15 µA)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and OE options  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
• Available in Pb-free and non-Pb-free 32-pin (450  
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I  
Logic Block Diagram  
Pin Configuration  
Top View  
SOIC  
V
NC  
A
16  
32  
1
2
3
4
5
CC  
31  
30  
A
15  
CE  
A
14  
2
A
12  
29  
28  
27  
26  
I/O  
WE  
A
13  
0
INPUT BUFFER  
A
7
6
A
A
I/O  
I/O  
6
8
1
2
A
A
A
0
1
2
7
8
9
10  
11  
12  
13  
14  
A
5
A
9
A
11  
OE  
25  
24  
23  
22  
21  
20  
19  
A
4
A
3
A
A
A
A
A
A
3
4
5
6
7
8
A
A
I/O  
I/O  
I/O  
2
128K x 8  
ARRAY  
10  
3
4
5
A
CE  
1
I/O  
I/O  
6
I/O  
5
1
A
7
0
I/O  
0
I/O  
1
15  
I/O  
GN  
G
GgNncD  
18  
17  
I/O  
I/O  
3
2
4
16  
I/O  
I/O  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
CE  
WE  
1
2
OE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06498 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 3, 2006  
[+] Feedback  

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